SoC STA/Timing Design Engineer — Tapeout & Impact

A leading technology company in California is seeking an experienced SoC Physical Design Engineer responsible for the physical implementation of design partitions for complex SOCs. You will work closely with design teams to debug and improve timing, create methodologies, and perform deep analysis of timing paths. The role requires a minimum of a Bachelor's degree and over 10 years of relevant experience. Competitive salary ranges from $171,600 to $302,200 depending on qualifications and experience, along with comprehensive benefits including medical coverage and stock options. #J-18808-Ljbffr