Senior Physical Verification Applications Engineer (Hybrid)

A leading semiconductor manufacturer seeks a Senior Physical Verification Application Engineer in Phoenix, AZ. This role involves providing technical support in layout verification, developing technical content, and leading verification methodology for advanced CMOS processes. Ideal candidates will have a degree in Electrical/Computer Engineering and experience with EDA tools. The position offers competitive pay, opportunities for professional development, and eligibility for a hybrid work model. #J-18808-Ljbffr