Senior Physical Verification Engineer - Tape-out Lead

A global semiconductor company based in Phoenix is seeking a Senior Physical Verification Application Engineer to provide specialized support in layout verification and parasitic extraction for customers in the aerospace and defense sectors. The role involves collaboration with design teams to resolve complex verification challenges and improve customer satisfaction through expert guidance. Ideal candidates will have at least 5 years of experience with advanced CMOS processes, effective problem-solving skills, and the ability to obtain a US Government Security Clearance. #J-18808-Ljbffr