Senior ASIC Verification Engineer - Lead SystemVerilog/UVM

A leading semiconductor solutions provider is seeking a Senior Design Verification Engineer to ensure the correctness of complex ASIC designs. The role involves developing verification plans, creating testbenches using SystemVerilog/UVM, and collaborating with design engineers. Candidates should have a Bachelor's or Master's degree in Electrical Engineering and over 5 years of relevant experience. This position offers opportunities for professional growth in a supportive environment prioritizing performance and well-being. #J-18808-Ljbffr