ASIC Physical Design Staff Engineer in Tan Binh district

Alternate Job Titles: ASIC Physical Design Staff Engineer Staff ASIC Physical Design Specialist Physical Design Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a skilled and motivated ASIC physical design professional with a strong background in deep submicron design, recent tape-out experience, and the drive to contribute to innovative projects. You thrive in collaborative environments, communicate clearly in English, and have hands-on expertise with PNR, extraction, timing, and physical verification. Your scripting abilities (Perl, Tcl, Python) help automate and optimize workflows, and you’re eager to grow alongside a world-class engineering team. What You’ll Be Doing: Performing RTL-to-GDSII physical design for ASICs at block and chip level Executing PNR, extraction, timing closure, and physical verification (LVS/DRC) Automating design flows with scripting languages Collaborating with cross-functional teams to resolve design and integration issues Participating in design reviews and methodology improvements Documenting processes and sharing best practices The Impact You Will Have: Delivering high-quality, on-time silicon designs Driving innovation in design flows and methodologies Ensuring first-pass success for critical projects Supporting knowledge sharing and team growth Enabling next-generation tech in automotive, AI, and more Shaping the future of semiconductor design What You’ll Need: MSEE (or equivalent) with 4+ years of hands-on physical design experience, including recent tape-out contributions. Strong understanding of PNR, Extraction, Timing Analysis, and Physical Verification (LVS/DRC). Expertise in the full ASIC design cycle from RTL to GDSII at both block and chip levels. Proficiency in scripting languages such as Perl, Tcl, and Python for design automation and flow optimization. Solid engineering understanding of deep submicron design concepts and implementation flows. Good command of English (spoken and written) for effective communication in a global environment. Experience with testchip development and methodology (preferred, but not required). Who You Are: Analytical, detail-oriented, and collaborative Effective communicator Proactive and adaptable Resilient and accountable The Team You’ll Be A Part Of: Join a forward-thinking physical design team committed to excellence, knowledge sharing, and breakthrough silicon solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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