Datum Technologies Group
US_West | Network Design Engineer_L3
Datum Technologies Group, Springfield, Illinois, us, 62777
Job Title: Logic (RTL) Design Engineer
Location:
Santa Clara, CA (Hybrid potential; no remote)
Position Overview: We are seeking a highly experienced
Logic (RTL) Design Engineer
with deep expertise in block-level design, RTL coding, and physical implementation collaboration.
Key Responsibilities:
Design and develop RTL blocks based on system specifications. Perform RTL coding, Lint, CDC checks, and create timing constraint files. Collaborate with Synthesis, STA, PD, and DFT teams to meet performance, power, and area targets. Develop low-power designs using UPF/CPF methodologies. Conduct static checks (Lint, CDC using Spyglass), synthesis, LEC, and STA. Assist verification teams with debugging and support PD with timing constraints. Perform top-level RTL integration of clocks, resets, and configuration registers. Drive and complete tasks with minimal oversight.
Required Qualifications:
Bachelor's degree in electrical or computer engineering (or related field). Minimum 7+ years of RTL design experience. Strong knowledge of VLSI and digital design fundamentals. Proficiency in Verilog/SystemVerilog/VHDL. Experience with RTL development, integration, and CDC/Lint tools.
Preferred Qualifications:
Experience with GPIO, UART, SPI, SW, JTAG, I2C Ips. Familiarity with protocols such as AMBA/OCP, PCIe, USB, Ethernet. Knowledge of JESD204C block design and 3rd party IP/PHY integration. Understanding of DFT concepts and their impact on RTL. Strong scripting skills (Python, Perl, TCL). Effective communication and ability to collaborate with remote/global teams. Data-driven approach to design methodology and tool optimization.
Tool Proficiency (Preference Level: 1-5):
Synopsys/Cadence EDA Tools
- 5 Design Compiler
- 5 Spyglass
- 5 Python
- 3
"All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran."
Santa Clara, CA (Hybrid potential; no remote)
Position Overview: We are seeking a highly experienced
Logic (RTL) Design Engineer
with deep expertise in block-level design, RTL coding, and physical implementation collaboration.
Key Responsibilities:
Design and develop RTL blocks based on system specifications. Perform RTL coding, Lint, CDC checks, and create timing constraint files. Collaborate with Synthesis, STA, PD, and DFT teams to meet performance, power, and area targets. Develop low-power designs using UPF/CPF methodologies. Conduct static checks (Lint, CDC using Spyglass), synthesis, LEC, and STA. Assist verification teams with debugging and support PD with timing constraints. Perform top-level RTL integration of clocks, resets, and configuration registers. Drive and complete tasks with minimal oversight.
Required Qualifications:
Bachelor's degree in electrical or computer engineering (or related field). Minimum 7+ years of RTL design experience. Strong knowledge of VLSI and digital design fundamentals. Proficiency in Verilog/SystemVerilog/VHDL. Experience with RTL development, integration, and CDC/Lint tools.
Preferred Qualifications:
Experience with GPIO, UART, SPI, SW, JTAG, I2C Ips. Familiarity with protocols such as AMBA/OCP, PCIe, USB, Ethernet. Knowledge of JESD204C block design and 3rd party IP/PHY integration. Understanding of DFT concepts and their impact on RTL. Strong scripting skills (Python, Perl, TCL). Effective communication and ability to collaborate with remote/global teams. Data-driven approach to design methodology and tool optimization.
Tool Proficiency (Preference Level: 1-5):
Synopsys/Cadence EDA Tools
- 5 Design Compiler
- 5 Spyglass
- 5 Python
- 3
"All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran."