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Veracity

Principal Analog Mixed-Signal Design Engineer - RF / SiPho / TIA / CMOS / SiGe

Veracity, Westlake Village, California, United States, 91361

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Principal Analog Mixed-Signal Design Engineer - RF / SiPho / TIA / CMOS / SiGe

Hybrid

- 2.5 days a week minimum in office

Westlake Village, CA, US

Seeking an RF and Analog Design Engineer to contribute to the development of multi-tens of GHz Transimpedance amplifiers TIAs. These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs best in class for coherent long-haul and metro systems as well as PAM4 data center systems.

In this role you will be responsible for: • ctive circuit design as well as technical leadership. • Design leading edge transimpedance amplifier design, primarily in Silicon Germanium (SiGe) BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology, where circuit performance will need to transcend beyond industry leading products. • Develop transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable. • Design of hi-performance broadband analog circuits for optical front-end receivers. • Design of various other analog circuits including linear regulators, AGC loop, current/voltage sensors, bandgaps etc. • Develop microarchitecture of major circuit blocks and guide team of designers to implement them. Work with various technologies including SiGe BiCMOS and CMOS. • Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support.

What We're Looking For

Bachelor's degree in Electrical Engineering in the areas of design of high-performance

RF/Analog Receiver/TIA design

and 10 - 15 years' experience Or MSc EE Or PhD EE with 5+ years of experience in the areas of design of high-performance

RF/Analog Receiver/TIA design . • Proven experience in IC design including chip tape-out AND lab evaluation of receiver design working in the industry). • Solid experience in.

o Using EDA CAD tools

o Performing Analog Custom Layout • Experience in measuring IC performance and debug of design to correlate simulations to measurements • Deep understanding of fundamentals, including:

o Detailed transistor level design

o Device physics

o Control/Feedback loop stability analysis • Direct project experience in at least one of the following areas is a plus:

o GC loop design

o High precision analog circuits (Including linear regulators, current sensors, bandgaps and DAC/Client)

o Experience in CTLE design • Experience in Package-System integration issues desired • Project experience in using different technologies. (SiGe BiCMOS is a plus) • team-player • Experience in the following is a strong plus:

o Overseeing and mentoring junior circuit designers

o Experience as chip lead with success in silicon

o Experience in taking chips to mass production

o bility to translate chip level specifications into architecture • Strong communication, presentation and documentation skills.