Motion Recruitment
Jr. - Sr. - DSP R&D Engineer - Commnuication Algorithm, Ethernet PHY,
Motion Recruitment, Irvine, California, United States, 92713
Our client is a global infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications.
They are urgently seeking multiple engineers from - Jr. PhD graduates with Solid therotical & relevant DSP experience - Mid-level MS degrees with 5+ years in DSP and commubication algorithm development knowledge and experience and Ethernet PHY design - Sr. level Digital Signal Processing (DSP) R&D Engineer with Ethernet and WIRELINE to join their growing team.
Responsibilities include: • Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms • Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation • Develop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulations • Define and document chip requirements, architecture, verification and lab test plan • Lab testing and debug of ASICs • Documentation/application note development and customer support
Requirements: • BS Degree with 10+ years experience, Master's and 3+ years of related experience; or PhD in Digital Signal Processing • Knowledge in Communication Theory & Digital Signal Processing algorithms • Experience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithms • Experience in C/C++, MATLAB/Simulink, • Experience architecting communications systems for high performance ASIC based products is highly desirable • Good hands-on skills in the lab • Good oral and written communication skills •
Experience in Wireline Algorithms - • Experience in Ethernet 802.3 PHY Transceivers
The Offer : - 140-200K - full medical, dental, Vision - 401K - PTO - Bonus potential
Motion Recruitment Partners
Posted by:
Kevin Gabrielson
Specialization :
Network Engineering Embedded
They are urgently seeking multiple engineers from - Jr. PhD graduates with Solid therotical & relevant DSP experience - Mid-level MS degrees with 5+ years in DSP and commubication algorithm development knowledge and experience and Ethernet PHY design - Sr. level Digital Signal Processing (DSP) R&D Engineer with Ethernet and WIRELINE to join their growing team.
Responsibilities include: • Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms • Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation • Develop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulations • Define and document chip requirements, architecture, verification and lab test plan • Lab testing and debug of ASICs • Documentation/application note development and customer support
Requirements: • BS Degree with 10+ years experience, Master's and 3+ years of related experience; or PhD in Digital Signal Processing • Knowledge in Communication Theory & Digital Signal Processing algorithms • Experience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithms • Experience in C/C++, MATLAB/Simulink, • Experience architecting communications systems for high performance ASIC based products is highly desirable • Good hands-on skills in the lab • Good oral and written communication skills •
Experience in Wireline Algorithms - • Experience in Ethernet 802.3 PHY Transceivers
The Offer : - 140-200K - full medical, dental, Vision - 401K - PTO - Bonus potential
Motion Recruitment Partners
Posted by:
Kevin Gabrielson
Specialization :
Network Engineering Embedded