獰慣數
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
LEAD ASIC VERIFICATION ENGINEER
OVERVIEW: This position requires technical project leadership, the ability to lead a team and derive system requirements. The candidate must have experience leading several ASIC verification efforts with team sizes of 3 engineers or larger. The candidate must have at least 8 years of System Verilog experience in an UVM development environment. The position requires excellent communication and documentation skills. The position will require the candidate to develop functional verification/validation tests to verify fairly complex systems will meet design requirements. The candidate will create test plans for RTL validation, defining and running system simulation models, collecting coverage report, and finding and implementing corrective measures for failing RTL tests. The candidate will also analyze and use results to modify testing. RESPONSIBILITIES:
Develop the actual UVM DV Agent (Monitor, Driver, ScoreBoard) Write comprehensive verification test plans Derive, generate, and track the coverage metrics Develop SystemVerilog/UVM testbenches at Top/Sub-system/Block-levels Debug, report, and work closely with design engineers Communicate with the team and execute the test plans in timely manner Develop Re-usable UVM Verification IPs or UVM Verification Components (UVC) Develop/Integrate C/C++/Matlab Reference models into the testbench Develop/Modify Perl/Bash/Python scripts Collecting and Closing on all functional coverage analysis and enhance the test case to cover the coverage gap. Lead, mentor, and Direct more engineers on the team, manage and track verification development schedules BASIC QUALIFICATIONS:
Bachelor of Science in Electrical Engineering or Computer Science 8+ years of experience VMM/OVM/UVM development in verification on unix-based platforms Team Leadership & project ownership, the candidate must have lead verification teams of 3 or more in the past. 8+ years of experience in Code coverage, also constrained random and directed test development and coverage specification and analysis Must have verified at least 5 production ASICs PREFERRED SKILLS AND EXPERIENCE:
Masters of Science or PhD in Electrical Engineering or Computer Science Expert level knowledge of test bench development using Object Oriented System Verilog Building complete UVM based test bench environments from scratch. Developing Drivers, Monitors, Sequencers, Agents, Scoreboards, Checkers, etc Proficient in System Verilog Experience with automated regression test development Detailed experience in shell programming language such as bash, csh, KSh, sh Detailed experience in scripting language such as Perf, Perl, TCL, SED, Python, make file, etc. ASIC test plan development, definition, and specification Excellent problem solving skills BFM development for a wide variety of common embedded processors Experience with emulation platform (like Mentor Veloce or Cadence Palladium) Experienced with porting other language models (like Matlab Models) in verification environment Cache Architectures Formal verification using Conformal and/or Formality Verification of mixed signal, and wireless communication ASICs Lab experience with logic analyzers and oscilloscopes Logic Synthesis: Design Compiler, Test Compiler, Prime Time, RC RTL compiler Revision Control Systems: perforce, svn, cvs, git, clearcase ADDITIONAL REQUIREMENTS:
Must be available to work extended hours and weekends as needed ITAR REQUIREMENTS:
To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.
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OVERVIEW: This position requires technical project leadership, the ability to lead a team and derive system requirements. The candidate must have experience leading several ASIC verification efforts with team sizes of 3 engineers or larger. The candidate must have at least 8 years of System Verilog experience in an UVM development environment. The position requires excellent communication and documentation skills. The position will require the candidate to develop functional verification/validation tests to verify fairly complex systems will meet design requirements. The candidate will create test plans for RTL validation, defining and running system simulation models, collecting coverage report, and finding and implementing corrective measures for failing RTL tests. The candidate will also analyze and use results to modify testing. RESPONSIBILITIES:
Develop the actual UVM DV Agent (Monitor, Driver, ScoreBoard) Write comprehensive verification test plans Derive, generate, and track the coverage metrics Develop SystemVerilog/UVM testbenches at Top/Sub-system/Block-levels Debug, report, and work closely with design engineers Communicate with the team and execute the test plans in timely manner Develop Re-usable UVM Verification IPs or UVM Verification Components (UVC) Develop/Integrate C/C++/Matlab Reference models into the testbench Develop/Modify Perl/Bash/Python scripts Collecting and Closing on all functional coverage analysis and enhance the test case to cover the coverage gap. Lead, mentor, and Direct more engineers on the team, manage and track verification development schedules BASIC QUALIFICATIONS:
Bachelor of Science in Electrical Engineering or Computer Science 8+ years of experience VMM/OVM/UVM development in verification on unix-based platforms Team Leadership & project ownership, the candidate must have lead verification teams of 3 or more in the past. 8+ years of experience in Code coverage, also constrained random and directed test development and coverage specification and analysis Must have verified at least 5 production ASICs PREFERRED SKILLS AND EXPERIENCE:
Masters of Science or PhD in Electrical Engineering or Computer Science Expert level knowledge of test bench development using Object Oriented System Verilog Building complete UVM based test bench environments from scratch. Developing Drivers, Monitors, Sequencers, Agents, Scoreboards, Checkers, etc Proficient in System Verilog Experience with automated regression test development Detailed experience in shell programming language such as bash, csh, KSh, sh Detailed experience in scripting language such as Perf, Perl, TCL, SED, Python, make file, etc. ASIC test plan development, definition, and specification Excellent problem solving skills BFM development for a wide variety of common embedded processors Experience with emulation platform (like Mentor Veloce or Cadence Palladium) Experienced with porting other language models (like Matlab Models) in verification environment Cache Architectures Formal verification using Conformal and/or Formality Verification of mixed signal, and wireless communication ASICs Lab experience with logic analyzers and oscilloscopes Logic Synthesis: Design Compiler, Test Compiler, Prime Time, RC RTL compiler Revision Control Systems: perforce, svn, cvs, git, clearcase ADDITIONAL REQUIREMENTS:
Must be available to work extended hours and weekends as needed ITAR REQUIREMENTS:
To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.
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