Hudson River Trading
Join to apply for the
Design Verification (DV) Engineer
role at
Hudson River Trading Join to apply for the
Design Verification (DV) Engineer
role at
Hudson River Trading The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs Managing test suites and continuous integration infrastructure Developing and improving open-source and internal tools
Qualifications
Superb debug and analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage collection/analysis Experience with SystemVerilog and industry-standard frameworks such as UVM Experience with Python Comfortable in a Linux environment Familiarity with Verilator and/or Cocotb preferred C++ experience is a plus A bachelor’s degree in computer science, electrical engineering, or a related field
Culture
Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We’re a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization—from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we’re friends and colleagues – whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we’d love to get to know you. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Finance Industries Capital Markets Referrals increase your chances of interviewing at Hudson River Trading by 2x Get notified about new Design Verification Engineer jobs in
Austin, TX . Austin, TX $114,000.00-$133,000.00 2 weeks ago Austin, TX $114,000.00-$166,000.00 2 weeks ago Austin, TX $114,000.00-$166,000.00 2 weeks ago CPU Functional Verification Engineer, Silicon, University Graduate
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Austin, Texas Metropolitan Area 3 days ago Austin, Texas Metropolitan Area 5 days ago Austin, TX $220,000.00-$240,000.00 2 weeks ago Austin, TX $104,000.00-$212,200.00 2 days ago Austin, TX $142,000.00-$203,000.00 2 weeks ago Austin, TX $173,000.00-$249,000.00 2 weeks ago Austin, TX $212,000.00-$291,000.00 2 weeks ago SOC Design Verification Engineer, Self-Driving
CPU Verification Engineer (Multiple Locations)
Austin, TX $139,000.00-$234,500.00 1 week ago Austin, TX $130,355.00-$221,603.00 1 week ago ASIC Physical Design Engineer, Annapurna Labs
Austin, Texas Metropolitan Area 1 month ago Austin, TX $140,000.00-$229,800.00 3 weeks ago Austin, TX $173,000.00-$249,000.00 2 weeks ago Austin, TX $139,360.00-$209,040.00 2 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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Design Verification (DV) Engineer
role at
Hudson River Trading Join to apply for the
Design Verification (DV) Engineer
role at
Hudson River Trading The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs Managing test suites and continuous integration infrastructure Developing and improving open-source and internal tools
Qualifications
Superb debug and analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage collection/analysis Experience with SystemVerilog and industry-standard frameworks such as UVM Experience with Python Comfortable in a Linux environment Familiarity with Verilator and/or Cocotb preferred C++ experience is a plus A bachelor’s degree in computer science, electrical engineering, or a related field
Culture
Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We’re a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization—from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we’re friends and colleagues – whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we’d love to get to know you. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Finance Industries Capital Markets Referrals increase your chances of interviewing at Hudson River Trading by 2x Get notified about new Design Verification Engineer jobs in
Austin, TX . Austin, TX $114,000.00-$133,000.00 2 weeks ago Austin, TX $114,000.00-$166,000.00 2 weeks ago Austin, TX $114,000.00-$166,000.00 2 weeks ago CPU Functional Verification Engineer, Silicon, University Graduate
Austin, TX $108,000.00-$158,000.00 1 week ago Austin, TX $212,000.00-$291,000.00 2 weeks ago Austin, TX $142,000.00-$203,000.00 2 weeks ago Austin, TX $114,000.00-$166,000.00 2 weeks ago Fall Co-Op - Digital Design Engineer (FF)
Austin, Texas Metropolitan Area 3 days ago Austin, Texas Metropolitan Area 5 days ago Austin, TX $220,000.00-$240,000.00 2 weeks ago Austin, TX $104,000.00-$212,200.00 2 days ago Austin, TX $142,000.00-$203,000.00 2 weeks ago Austin, TX $173,000.00-$249,000.00 2 weeks ago Austin, TX $212,000.00-$291,000.00 2 weeks ago SOC Design Verification Engineer, Self-Driving
CPU Verification Engineer (Multiple Locations)
Austin, TX $139,000.00-$234,500.00 1 week ago Austin, TX $130,355.00-$221,603.00 1 week ago ASIC Physical Design Engineer, Annapurna Labs
Austin, Texas Metropolitan Area 1 month ago Austin, TX $140,000.00-$229,800.00 3 weeks ago Austin, TX $173,000.00-$249,000.00 2 weeks ago Austin, TX $139,360.00-$209,040.00 2 days ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr