TEEMA Solutions Group
About the Opportunity
Initio Capital is hiring
DFT Engineers
on behalf of a stealth-mode compute systems company that’s architecting
RISC-V–based chips purpose-built for AI, analytics, and next-generation server workloads . With deep technical leadership and backing from top-tier investors, this company is pushing the boundaries of power-efficient, secure, and performance-optimized compute. As a
Design-for-Test Engineer , you’ll help ensure silicon reliability and debug-readiness from the earliest design stages through post-silicon validation. About the Role
This is a
high-ownership, full-cycle DFT role . You’ll work on scan insertion, MBIST, JTAG, ATPG, and IEEE1500 implementations from unit-level RTL through SoC integration and silicon bring-up. Your work will directly impact yield, test coverage, and in-field diagnosability across the chip lifecycle. You'll collaborate cross-functionally with design, verification, and physical design teams to architect scalable test strategies for cutting-edge compute silicon. What You’ll Do
Define and implement DFT strategy across CPU, IP, and SoC levels Design and verify DFT features including scan, MBIST, BIST, ATPG, and boundary scan Integrate DFT features into RTL and validate across simulation and synthesis flows Own post-layout verification and work closely with physical design teams to meet DFT constraints Support test pattern generation, debug, and post-silicon validation Contribute to continuous improvements in test coverage, area/power overheads, and automation flows What We’re Looking For
5+ years of hands-on experience in
DFT architecture, design, and verification Proficient in Verilog/SystemVerilog for RTL and test logic design Solid knowledge of
scan insertion ,
MBIST ,
ATPG ,
JTAG , and
IEEE1500
standards Experience debugging with waveform tools (e.g., Verdi, SimVision) and simulation environments Familiarity with synthesis, formal verification, and timing closure for DFT flows Proven ability to collaborate with PD and architecture teams in a fast-paced silicon environment Experience closing DFT across advanced process nodes (7nm/5nm) Prior work on CPU/SoC test architecture Familiarity with post-layout and boundary scan validation techniques History of working in high-performance server or AI chip design environments Equity:
Meaningful early-stage grant Hybrid in
Santa Clara, CA H-1B, O-1, and OPT sponsorship available Join a world-class team solving hard, foundational problems in modern silicon Play a key role in the development of secure, efficient next-gen compute platforms If you’re ready to lead DFT at the chip level for a company building the future of compute—this is your opportunity. Apply now to join a stealth rocket ship redefining performance and testability in silicon.
#J-18808-Ljbffr
Initio Capital is hiring
DFT Engineers
on behalf of a stealth-mode compute systems company that’s architecting
RISC-V–based chips purpose-built for AI, analytics, and next-generation server workloads . With deep technical leadership and backing from top-tier investors, this company is pushing the boundaries of power-efficient, secure, and performance-optimized compute. As a
Design-for-Test Engineer , you’ll help ensure silicon reliability and debug-readiness from the earliest design stages through post-silicon validation. About the Role
This is a
high-ownership, full-cycle DFT role . You’ll work on scan insertion, MBIST, JTAG, ATPG, and IEEE1500 implementations from unit-level RTL through SoC integration and silicon bring-up. Your work will directly impact yield, test coverage, and in-field diagnosability across the chip lifecycle. You'll collaborate cross-functionally with design, verification, and physical design teams to architect scalable test strategies for cutting-edge compute silicon. What You’ll Do
Define and implement DFT strategy across CPU, IP, and SoC levels Design and verify DFT features including scan, MBIST, BIST, ATPG, and boundary scan Integrate DFT features into RTL and validate across simulation and synthesis flows Own post-layout verification and work closely with physical design teams to meet DFT constraints Support test pattern generation, debug, and post-silicon validation Contribute to continuous improvements in test coverage, area/power overheads, and automation flows What We’re Looking For
5+ years of hands-on experience in
DFT architecture, design, and verification Proficient in Verilog/SystemVerilog for RTL and test logic design Solid knowledge of
scan insertion ,
MBIST ,
ATPG ,
JTAG , and
IEEE1500
standards Experience debugging with waveform tools (e.g., Verdi, SimVision) and simulation environments Familiarity with synthesis, formal verification, and timing closure for DFT flows Proven ability to collaborate with PD and architecture teams in a fast-paced silicon environment Experience closing DFT across advanced process nodes (7nm/5nm) Prior work on CPU/SoC test architecture Familiarity with post-layout and boundary scan validation techniques History of working in high-performance server or AI chip design environments Equity:
Meaningful early-stage grant Hybrid in
Santa Clara, CA H-1B, O-1, and OPT sponsorship available Join a world-class team solving hard, foundational problems in modern silicon Play a key role in the development of secure, efficient next-gen compute platforms If you’re ready to lead DFT at the chip level for a company building the future of compute—this is your opportunity. Apply now to join a stealth rocket ship redefining performance and testability in silicon.
#J-18808-Ljbffr