Ampere Computing LLC.
Principal Physical Design Verification/ESD Engineer
Ampere Computing LLC., Portland, Oregon, United States, 97204
Principal Physical Design Verification/ESD Engineer
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Principal Physical Design Verification/ESD Engineer
role at
Ampere . About the Role As a member of the PDV Team, you'll own chip-level physical design verification, flow automation, reviews, and ESD coverage. Responsibilities include: Partition and chip-level ownership of physical design verification and reviews. Execute and debug verification flows for GDS tape-out on FinFET designs. ESD verification and sign-off at partition and chip levels. Design enhancements and DFM techniques. Package level physical verification. LVS/DRC check coding. Support PDV sign-off scripts at partition and chip levels. Collaborate across multiple sites, including US, India, and Vietnam. Qualifications: Experience with FinFets and multi-exposure metallization. Familiarity with Cadence and Siemens tools. Knowledge of Shell, Skill, Calibre, and scripting. Experience with flow automation and ESD verification flows. Understanding of DFM techniques for yield enhancement. Ability to address chip-level issues like density, latch-up failures, and nets. Bachelor’s in Electrical or Computer Engineering with 8+ years, or Master’s with 6+ years, or PhD with 3+ years of experience. Benefits: Competitive salary ranging from $140,500 to $234,500, higher in San Francisco Bay Area. Comprehensive health, dental, vision, and retirement plans. Unlimited flextime, paid holidays, and wellness programs. Inclusive culture promoting growth and innovation. Ampere is an equal opportunity employer, welcoming applicants from all backgrounds.
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Join to apply for the
Principal Physical Design Verification/ESD Engineer
role at
Ampere . About the Role As a member of the PDV Team, you'll own chip-level physical design verification, flow automation, reviews, and ESD coverage. Responsibilities include: Partition and chip-level ownership of physical design verification and reviews. Execute and debug verification flows for GDS tape-out on FinFET designs. ESD verification and sign-off at partition and chip levels. Design enhancements and DFM techniques. Package level physical verification. LVS/DRC check coding. Support PDV sign-off scripts at partition and chip levels. Collaborate across multiple sites, including US, India, and Vietnam. Qualifications: Experience with FinFets and multi-exposure metallization. Familiarity with Cadence and Siemens tools. Knowledge of Shell, Skill, Calibre, and scripting. Experience with flow automation and ESD verification flows. Understanding of DFM techniques for yield enhancement. Ability to address chip-level issues like density, latch-up failures, and nets. Bachelor’s in Electrical or Computer Engineering with 8+ years, or Master’s with 6+ years, or PhD with 3+ years of experience. Benefits: Competitive salary ranging from $140,500 to $234,500, higher in San Francisco Bay Area. Comprehensive health, dental, vision, and retirement plans. Unlimited flextime, paid holidays, and wellness programs. Inclusive culture promoting growth and innovation. Ampere is an equal opportunity employer, welcoming applicants from all backgrounds.
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