Astera Labs
Technical Lead Design Verification Engineer
Astera Labs, San Jose, California, United States, 95199
Technical Lead Design Verification Engineer
Join to apply for the
Technical Lead Design Verification Engineer
role at
Astera Labs Technical Lead Design Verification Engineer
1 week ago Be among the first 25 applicants Join to apply for the
Technical Lead Design Verification Engineer
role at
Astera Labs Get AI-powered advice on this job and more exclusive features. Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at
www.asteralabs.com
.
We are looking for
Senior Design Verification Engineers
with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic Qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred. ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately.
Required Experience
Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.
Preferred Experience
Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods.
The base salary range is USD 147,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Design, Art/Creative, and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Astera Labs by 2x Get notified about new Design Technician jobs in
San Jose, CA . San Carlos, CA $82,000.00-$109,300.00 18 hours ago San Jose, CA $76,000.00-$98,000.00 1 week ago San Jose, CA $76,000.00-$101,500.00 1 week ago Pleasanton, CA $76,000.00-$98,000.00 1 week ago Redwood City, CA $76,000.00-$98,000.00 1 week ago Pleasanton, CA $76,000.00-$101,500.00 1 week ago Menlo Park, CA $165,000.00-$231,000.00 2 weeks ago Product Design Engineer, In House Cell Engineering
Santa Clara, CA $152,000.00-$208,500.00 6 days ago Mechanical Design Engineer (Tooling Design Focus)
Santa Clara, CA $100,000.00-$175,000.00 5 days ago Santa Clara, CA $108,000.00-$212,750.00 2 days ago Menlo Park, CA $173,000.00-$249,000.00 2 weeks ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Union City, CA $100,000.00-$120,000.00 2 weeks ago San Jose, CA $134,400.00-$168,000.00 1 day ago San Jose, CA $194,000.00-$410,000.00 11 hours ago San Jose, CA $134,400.00-$168,000.00 1 day ago San Jose, CA $185,000.00-$230,000.00 4 days ago San Carlos, CA $95,000.00-$145,000.00 1 month ago Sunnyvale, CA $103,000.00-$158,500.00 1 week ago Internship, Mechanical Design Engineer, Vehicle Engineering (Winter/Spring 2026)
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr
Join to apply for the
Technical Lead Design Verification Engineer
role at
Astera Labs Technical Lead Design Verification Engineer
1 week ago Be among the first 25 applicants Join to apply for the
Technical Lead Design Verification Engineer
role at
Astera Labs Get AI-powered advice on this job and more exclusive features. Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at
www.asteralabs.com
.
We are looking for
Senior Design Verification Engineers
with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic Qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred. ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately.
Required Experience
Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.
Preferred Experience
Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods.
The base salary range is USD 147,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Design, Art/Creative, and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Astera Labs by 2x Get notified about new Design Technician jobs in
San Jose, CA . San Carlos, CA $82,000.00-$109,300.00 18 hours ago San Jose, CA $76,000.00-$98,000.00 1 week ago San Jose, CA $76,000.00-$101,500.00 1 week ago Pleasanton, CA $76,000.00-$98,000.00 1 week ago Redwood City, CA $76,000.00-$98,000.00 1 week ago Pleasanton, CA $76,000.00-$101,500.00 1 week ago Menlo Park, CA $165,000.00-$231,000.00 2 weeks ago Product Design Engineer, In House Cell Engineering
Santa Clara, CA $152,000.00-$208,500.00 6 days ago Mechanical Design Engineer (Tooling Design Focus)
Santa Clara, CA $100,000.00-$175,000.00 5 days ago Santa Clara, CA $108,000.00-$212,750.00 2 days ago Menlo Park, CA $173,000.00-$249,000.00 2 weeks ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Union City, CA $100,000.00-$120,000.00 2 weeks ago San Jose, CA $134,400.00-$168,000.00 1 day ago San Jose, CA $194,000.00-$410,000.00 11 hours ago San Jose, CA $134,400.00-$168,000.00 1 day ago San Jose, CA $185,000.00-$230,000.00 4 days ago San Carlos, CA $95,000.00-$145,000.00 1 month ago Sunnyvale, CA $103,000.00-$158,500.00 1 week ago Internship, Mechanical Design Engineer, Vehicle Engineering (Winter/Spring 2026)
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr