Join to apply for the Formal RTL Design Verification Engineer role at Condor Computing Corporation
Join to apply for the Formal RTL Design Verification Engineer role at Condor Computing Corporation
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Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry's highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing.
Formal Verification Engineer
As a Formal Verification Engineer at Condor, you will be responsible for ensuring the correctness and reliability of our world-class processor designs. Your role will involve crafting innovative solutions to verify complex design micro-architectures using cutting-edge technologies. Additionally, you will collaborate closely with design teams to enhance micro-architecture and contribute to the development of reusable and optimized verification models.
As a formal verification engineer with Condor, you will
- Work on verification of Condor's world-class processor designs
- Craft novel, creative, and best-in-class solutions for verifying complex design micro-architectures with the best technologies available
- Develop a comprehensive formal verification test plan
- Develop functional properties for the design, find design bugs, and work closely with design teams to help improve the micro-architecture
- Develop re-usable and optimized verification models and a verification code base
- Architect correct-by-construction design methodologies to enhance formal verification efficiency and productivity
- Master' Bachelor, or above degree in electronic/electrical engineering or computer science
- 4+ years of verification experience, with at least 2 years utilizing formal verification methods
- Solid understanding of RTL designs and computer architecture
- Proficiency in scripting languages such as Python, Ruby, or Perl
- Demonstrated track record of implementing new ideas that positively impact the company
- Industry experience developing test benches and verification components from scratch using SystemVerilog and UVM
- Deep understanding of event-driven simulator-based modeling techniques
- Familiarity with low-power implementation (UPF)
- Strong written and verbal communication skills
- Effective cross-site and cross-functional execution skill
We look forward to reviewing your application!
Seniority level
Seniority level
Mid-Senior level
Employment type
Employment type
Full-time
Job function
Job function
Engineering and Information TechnologyIndustries
Semiconductor Manufacturing
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