Tech Providers
- Develop and validate complex multi-mode/multi-corner timing constraints (SDC) for RTL and signoff
- Perform pre-route timing checks and QoR cleanup to ensure smooth STA handoff
- Debug and resolve timing violations using Synopsys Primetime/Design Compiler
- Automate flows using Tcl scripting to improve efficiency in constraint validation
- Analyze and fix RTL quality issues (Lint/CDC) early in design phase
- Execute timing regression and track progress for multimillion-gate ASIC designs