Senior Physical Design Engineer

Senior Physical Design Engineer
nFull-time + Benefits
nRichardson, Texas (onsite/hybrid)
nUS Citizen or US Permanent Resident
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nResponsibilities:
n• Architect system requirements
n• Collaborate effectively with the full ASIC design implementation team with a Humble, Hungry and Smart attitude
n• Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus| Innovus | Tempus
n• Plan budget, tools and team effort and champion project needs to ensure milestones and objectives are met
n• Super user of industry standard Physical Design, Synthesis and Timing Analysis tools
n• Accountable for physical design implementation of complex, low-power designs including physical-aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification
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nSkills / Experience:
n• BSEE/MSEE with 5+ years of related industry experience
n• 5+ years hands-on experience in high reliability, low power VLSI designs
n• 5+ years of experience with Cadence digital design tools (Genus, Innovus, Tempus)
n• Basic proficiency with programming languages such as Perl, C and TCL
n• Excellent understanding of reliability, test and power concepts & design tradeoffs required
n• ITAR compliance approval required
n• Knowledge of MIPI, I2S, CAN protocols a plus
n• Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
n• Production-proven experience with Floor planning at Chip Level with Bus/Pin variables, Synthesis, Place and Route Optimization, Parasitic Extraction, Static Timing Analysis, Low Power Intent (UPF/CPF), Power Analysis, IR drop analysis, electromigration, Physical Verification and Sign Off
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nPHYSICAL DESIGN GROUP on LinkedIn: