Broadcom
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High Speed SerDes RTL Design Engineer
role at
Broadcom 2 weeks ago Be among the first 25 applicants Join to apply for the
High Speed SerDes RTL Design Engineer
role at
Broadcom Get AI-powered advice on this job and more exclusive features. Job Description:
Experience, qualification, and soft skills, have you got everything required to succeed in this opportunity Find out below.
Broadcom is looking for a Master RTL Designer. In this highly visible role, you will be responsible for leading the design and development of highly integrated SerDes solutions for the next generation of AI connectivity.
MS or PhD in Electrical Engineering or Computer Engineering with 13+ years of experience in front end digital design for serial high-speed data center networking applications. Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications in advanced modulation formats. Experience in integrating the front end design with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification. Hands on experience in providing guidelines for design constraints generation and evaluating processes for backend development, floorplan, guidelines for Place and Route. Evaluating timing signoff, verification and IP Integration and system level verification. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Deep understanding of high-speed optical/electrical interconnect architectures such as 200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime. Experience in driving SOC level front end design specifications and other documentation in a clear and concise fashion. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have prior experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Job Description:
Broadcom is looking for a Master RTL Designer. In this highly visible role, you will be responsible for leading the design and development of highly integrated SerDes solutions for the next generation of AI connectivity.
Qualifications include:
MS or PhD in Electrical Engineering or Computer Engineering with 13+ years of experience in front end digital design for serial high-speed data center networking applications. Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications in advanced modulation formats. Experience in integrating the front end design with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification. Hands on experience in providing guidelines for design constraints generation and evaluating processes for backend development, floorplan, guidelines for Place and Route. Evaluating timing signoff, verification and IP Integration and system level verification. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Deep understanding of high-speed optical/electrical interconnect architectures such as 200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime. Experience in driving SOC level front end design specifications and other documentation in a clear and concise fashion. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have prior experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications:
System knowledge of current generation and next generation of silicon photonics-based transceiver architectures and standards. Good understanding of advanced packaging (2.5D / 3D) architectures. Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels. Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Excellent time and task management, and interpersonal skills. Willingness to travel when required.
Additional Job Description:
Compensation And Benefits
The annual base salary range for this position is $163,000 - $262,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Broadcom by 2x Sign in to set job alerts for “Design Engineer” roles. Sunnyvale, CA $139,000.00-$200,000.00 1 week ago Fremont, CA $139,000.00-$200,000.00 6 days ago Sunnyvale, CA $108,100.00-$182,900.00 3 weeks ago Santa Clara, CA $120,000.00-$180,000.00 1 month ago Product Design Mechanical Engineer, Reality Labs Sunnyvale, CA $204,000.00-$281,000.00 2 weeks ago San Jose, CA $130,000.00-$160,000.00 4 days ago Fremont, CA $204,000.00-$281,000.00 4 days ago Mechanical Manufacturing Engineer, Data Centers Sunnyvale, CA $96,000.00-$138,000.00 1 week ago San Jose, CA $120,000.00-$250,000.00 1 month ago Sunnyvale, CA $170,000.00-$240,000.00 1 week ago Mountain View, CA $181,000.00-$297,000.00 1 week ago Sunnyvale, CA $139,000.00-$200,000.00 1 week ago Mountain View, CA $94,050.00-$141,550.00 1 week ago Mechanical Engineer, Data Center Engineering Menlo Park, CA $204,000.00-$281,000.00 2 weeks ago Sunnyvale, CA $111,000.00-$164,000.00 1 week ago Sunnyvale, CA $111,000.00-$164,000.00 2 days ago Fremont, CA $70,000.00-$155,000.00 1 week ago Mechanical Engineer, Data Center Engineering Fremont, CA $204,000.00-$281,000.00 2 weeks ago Palo Alto, CA $110,000.00-$140,000.00 2 weeks ago Mechanical Product Design Engineer, Platforms, University Graduate Sunnyvale, CA $105,000.00-$151,000.00 1 week ago Mechanical Design Engineer (Tooling Design Focus) Santa Clara, CA $100,000.00-$175,000.00 13 hours ago Pleasanton, CA $85,000.00-$135,000.00 3 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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High Speed SerDes RTL Design Engineer
role at
Broadcom 2 weeks ago Be among the first 25 applicants Join to apply for the
High Speed SerDes RTL Design Engineer
role at
Broadcom Get AI-powered advice on this job and more exclusive features. Job Description:
Experience, qualification, and soft skills, have you got everything required to succeed in this opportunity Find out below.
Broadcom is looking for a Master RTL Designer. In this highly visible role, you will be responsible for leading the design and development of highly integrated SerDes solutions for the next generation of AI connectivity.
MS or PhD in Electrical Engineering or Computer Engineering with 13+ years of experience in front end digital design for serial high-speed data center networking applications. Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications in advanced modulation formats. Experience in integrating the front end design with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification. Hands on experience in providing guidelines for design constraints generation and evaluating processes for backend development, floorplan, guidelines for Place and Route. Evaluating timing signoff, verification and IP Integration and system level verification. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Deep understanding of high-speed optical/electrical interconnect architectures such as 200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime. Experience in driving SOC level front end design specifications and other documentation in a clear and concise fashion. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have prior experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Job Description:
Broadcom is looking for a Master RTL Designer. In this highly visible role, you will be responsible for leading the design and development of highly integrated SerDes solutions for the next generation of AI connectivity.
Qualifications include:
MS or PhD in Electrical Engineering or Computer Engineering with 13+ years of experience in front end digital design for serial high-speed data center networking applications. Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications in advanced modulation formats. Experience in integrating the front end design with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification. Hands on experience in providing guidelines for design constraints generation and evaluating processes for backend development, floorplan, guidelines for Place and Route. Evaluating timing signoff, verification and IP Integration and system level verification. Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. Deep understanding of high-speed optical/electrical interconnect architectures such as 200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime. Experience in driving SOC level front end design specifications and other documentation in a clear and concise fashion. Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule. Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development. Strong analytical thinking and problem-solving skills with excellent attention to details. Must be organized, self-motivated and able to work effectively across internal and end customers teams. Must have prior experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications:
System knowledge of current generation and next generation of silicon photonics-based transceiver architectures and standards. Good understanding of advanced packaging (2.5D / 3D) architectures. Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels. Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Excellent time and task management, and interpersonal skills. Willingness to travel when required.
Additional Job Description:
Compensation And Benefits
The annual base salary range for this position is $163,000 - $262,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Broadcom by 2x Sign in to set job alerts for “Design Engineer” roles. Sunnyvale, CA $139,000.00-$200,000.00 1 week ago Fremont, CA $139,000.00-$200,000.00 6 days ago Sunnyvale, CA $108,100.00-$182,900.00 3 weeks ago Santa Clara, CA $120,000.00-$180,000.00 1 month ago Product Design Mechanical Engineer, Reality Labs Sunnyvale, CA $204,000.00-$281,000.00 2 weeks ago San Jose, CA $130,000.00-$160,000.00 4 days ago Fremont, CA $204,000.00-$281,000.00 4 days ago Mechanical Manufacturing Engineer, Data Centers Sunnyvale, CA $96,000.00-$138,000.00 1 week ago San Jose, CA $120,000.00-$250,000.00 1 month ago Sunnyvale, CA $170,000.00-$240,000.00 1 week ago Mountain View, CA $181,000.00-$297,000.00 1 week ago Sunnyvale, CA $139,000.00-$200,000.00 1 week ago Mountain View, CA $94,050.00-$141,550.00 1 week ago Mechanical Engineer, Data Center Engineering Menlo Park, CA $204,000.00-$281,000.00 2 weeks ago Sunnyvale, CA $111,000.00-$164,000.00 1 week ago Sunnyvale, CA $111,000.00-$164,000.00 2 days ago Fremont, CA $70,000.00-$155,000.00 1 week ago Mechanical Engineer, Data Center Engineering Fremont, CA $204,000.00-$281,000.00 2 weeks ago Palo Alto, CA $110,000.00-$140,000.00 2 weeks ago Mechanical Product Design Engineer, Platforms, University Graduate Sunnyvale, CA $105,000.00-$151,000.00 1 week ago Mechanical Design Engineer (Tooling Design Focus) Santa Clara, CA $100,000.00-$175,000.00 13 hours ago Pleasanton, CA $85,000.00-$135,000.00 3 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr