TEEMA Solutions Group
Location:
Hybrid – Santa Clara, CA or Austin, TX
Increase your chances of reaching the interview stage by reading the complete job description and applying promptly. Type:
Full-Time |
Salary:
$150K–$300K + Competitive Equity Visa Sponsorship:
H-1B, O-1, OPT Available About the Opportunity Initio Capital is hiring a
Post-Silicon Performance Validation Engineer
on behalf of a stealth-mode deep tech startup that is building a new class of
RISC-V–based compute accelerators
optimized for machine learning, analytics, and data-centric workloads. Backed by top-tier investors and founded by silicon veterans, this startup is reimagining how accelerator hardware interfaces with real-world software demands. Your mission: validate and optimize silicon in the real world—ensuring every chip delivers on its performance-per-watt promise. About the Role You’ll be at the center of post-silicon validation—analyzing performance data, debugging system-level bottlenecks, and improving throughput and efficiency across diverse AI and server benchmarks. You’ll work hands-on with hardware bring-up, performance regression tools, and automation frameworks. This role is inherently cross-functional—blending systems-level thinking with deep technical execution across software, firmware, architecture, and silicon. What You’ll Do Validate accelerator silicon performance against real-world workloads and industry benchmarks (e.g., MLPerf) Build infrastructure to automate post-silicon validation pipelines Analyze power, thermal, and performance metrics to optimize system-level performance-per-watt Debug hardware/software interactions and cross-stack inefficiencies Collaborate with firmware, driver, architecture, and hardware teams to isolate and fix critical issues Own performance validation methodology from chip bring-up through production What We’re Looking For 5+ years of hands-on experience in
post-silicon validation ,
SoC bring-up , or
performance optimization Scripting ability in
Python
or similar (for automation, analysis, and reporting) Familiarity with power/performance modeling and system profiling tools Experience validating complex SoCs or accelerators in production settings Comfort working in a fast-paced, high-ownership startup environment Experience with
MLPerf
or similar industry-standard AI benchmarks Background in CPU/GPU/accelerator validation or performance tuning Prior work optimizing power-performance tradeoffs in silicon or firmware Strong written communication and ability to document findings for cross-functional teams Equity:
Competitive early-stage grant Hybrid work from
Santa Clara, CA
or
Austin, TX Sponsorship for H-1B, O-1, OPT Join a founding technical team solving deep performance challenges at the silicon frontier Work on real workloads that power the next generation of AI infrastructure If you want to see your work directly impact the performance of cutting-edge silicon deployed in high-stakes, real-world scenarios—this is your moment.
#J-18808-Ljbffr
Hybrid – Santa Clara, CA or Austin, TX
Increase your chances of reaching the interview stage by reading the complete job description and applying promptly. Type:
Full-Time |
Salary:
$150K–$300K + Competitive Equity Visa Sponsorship:
H-1B, O-1, OPT Available About the Opportunity Initio Capital is hiring a
Post-Silicon Performance Validation Engineer
on behalf of a stealth-mode deep tech startup that is building a new class of
RISC-V–based compute accelerators
optimized for machine learning, analytics, and data-centric workloads. Backed by top-tier investors and founded by silicon veterans, this startup is reimagining how accelerator hardware interfaces with real-world software demands. Your mission: validate and optimize silicon in the real world—ensuring every chip delivers on its performance-per-watt promise. About the Role You’ll be at the center of post-silicon validation—analyzing performance data, debugging system-level bottlenecks, and improving throughput and efficiency across diverse AI and server benchmarks. You’ll work hands-on with hardware bring-up, performance regression tools, and automation frameworks. This role is inherently cross-functional—blending systems-level thinking with deep technical execution across software, firmware, architecture, and silicon. What You’ll Do Validate accelerator silicon performance against real-world workloads and industry benchmarks (e.g., MLPerf) Build infrastructure to automate post-silicon validation pipelines Analyze power, thermal, and performance metrics to optimize system-level performance-per-watt Debug hardware/software interactions and cross-stack inefficiencies Collaborate with firmware, driver, architecture, and hardware teams to isolate and fix critical issues Own performance validation methodology from chip bring-up through production What We’re Looking For 5+ years of hands-on experience in
post-silicon validation ,
SoC bring-up , or
performance optimization Scripting ability in
Python
or similar (for automation, analysis, and reporting) Familiarity with power/performance modeling and system profiling tools Experience validating complex SoCs or accelerators in production settings Comfort working in a fast-paced, high-ownership startup environment Experience with
MLPerf
or similar industry-standard AI benchmarks Background in CPU/GPU/accelerator validation or performance tuning Prior work optimizing power-performance tradeoffs in silicon or firmware Strong written communication and ability to document findings for cross-functional teams Equity:
Competitive early-stage grant Hybrid work from
Santa Clara, CA
or
Austin, TX Sponsorship for H-1B, O-1, OPT Join a founding technical team solving deep performance challenges at the silicon frontier Work on real workloads that power the next generation of AI infrastructure If you want to see your work directly impact the performance of cutting-edge silicon deployed in high-stakes, real-world scenarios—this is your moment.
#J-18808-Ljbffr