Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists has developed a high-performance RISC-V CPU from scratch and shares a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are seeking an experienced engineer focused on Fabric / Memory Subsystem verification for high-performance CPUs. The role involves working on a server-class Fabric unit.
This position is hybrid, based out of Austin, TX, Santa Clara, CA, Boston, MA, or Toronto, Ontario.
Responsibilities:
- Functional and performance verification of the Fabric unit for a from-scratch high-performance CPU, working closely with Architecture and RTL teams.
- Develop detailed block-level verification plans for a high-performance Fabric.
- Design and develop reusable block-level testbench components in SystemVerilog, UVM, and C++, including microarchitectural models, monitors, and checkers.
- Develop random and directed stimulus that spans pre-silicon, emulation, and post-silicon domains.
- Evaluate and integrate open-source toolchains into the DV flow.
- Develop DV environment, tools, and infrastructure to enable functional verification for pre-silicon, emulation, and post-silicon.
- Collaborate with design, test, and post-silicon validation teams to ensure high-quality delivery of the Fabric / Memory Subsystem block.
Experience and Qualifications:
- BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience.
- Strong background in high-performance out-of-order CPU microarchitecture, especially load/store, caches, and memory subsystems.
- Experience working on Fabric for CPU or GPU-based systems; knowledge of protocols such as CHI, AXI, ACE, Tilelink, CMN.
- Architectural understanding of memory ordering, cache coherency, memory consistency, multi-processors, and fabric topologies.
- Significant experience debugging RTL and DV in simulation environments.
- Proficiency in verification methodologies and techniques—simulation/debug, TB development, stimulus, checking, coverage, tools.
- Experience with C++, SystemVerilog, UVM, scripting languages, Verilog, VHDL, and simulators like VCS, NC, Verilator.
- Strong problem-solving and debugging skills across various design hierarchies.
Compensation ranges from $100k to $500k, including base and variable components. Actual offers depend on experience, skills, education, background, and location.
We offer a highly competitive compensation package and benefits, and are an equal opportunity employer.
Due to U.S. Export Control laws, employment requires compliance with licensing regulations, including possible citizenship or residency documentation. Employment may be contingent upon U.S. export license approval.
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