Etched.ai, Inc.
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Job Summary
We are seeking a talented Computer Architect to join our architecture team and contribute to the design of next-generation AI accelerators. This role focuses on developing and optimizing compute architectures that deliver exceptional performance and efficiency for transformer workloads. You will work on cutting-edge architectural problems and performance modeling with deep cross-functional collaboration to bring innovative chip designs from concept to silicon.
Key Responsibilities
Microarchitecture & dataflow innovation:
Design and analyze chip architectures optimized for AI/ML workloads, with focus on throughput, latency, and power efficiency
Design next-generation silicon:
Contribute to power and area estimation methodologies for early-stage, next generation architectural exploration
Custom circuit development:
Create architectural specifications and interface definitions for compute blocks and subsystems
System‑level prototyping:
Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and ultimate optimization
Performance optimization:
Conduct architectural experiments using cycle-accurate simulators and analytical models
Cross‑functional collaboration:
Support integration efforts by providing architectural guidance and resolving design challenges
You may be a good fit if you have PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
5+ years of experience in computer architecture, ASIC design, or related fields
Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects
Experience with performance modeling and architectural simulation tools
Hands‑on experience designing and optimizing floating‑point datapaths or arithmetic‑intensive circuits and working with advanced process nodes.
Proficiency in Rust, C/C++, or Python for modeling and analysis
Knowledge of modern processor microarchitecture and design tradeoffs
Strong analytical and problem-solving skills with attention to detail
Excellent communication skills and ability to work in cross-functional teams
Strong candidates may also have experience with AI/ML accelerator architectures and dataflow optimization
RTL design and verification (Verilog/SystemVerilog)
Cycle-accurate simulation tools (gem5, SystemC, or custom simulators)
Power and performance analysis methodologies
ASIC design flow and physical design constraints
Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.)
Hands-on experience with tapeout and silicon bring-up
Base Compensation Range $200,000 - $265,000
Benefits Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of
$2,000/month
for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
How we’re different Etched believes in the
Bitter Lesson
. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
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Design and analyze chip architectures optimized for AI/ML workloads, with focus on throughput, latency, and power efficiency
Design next-generation silicon:
Contribute to power and area estimation methodologies for early-stage, next generation architectural exploration
Custom circuit development:
Create architectural specifications and interface definitions for compute blocks and subsystems
System‑level prototyping:
Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and ultimate optimization
Performance optimization:
Conduct architectural experiments using cycle-accurate simulators and analytical models
Cross‑functional collaboration:
Support integration efforts by providing architectural guidance and resolving design challenges
You may be a good fit if you have PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field
5+ years of experience in computer architecture, ASIC design, or related fields
Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects
Experience with performance modeling and architectural simulation tools
Hands‑on experience designing and optimizing floating‑point datapaths or arithmetic‑intensive circuits and working with advanced process nodes.
Proficiency in Rust, C/C++, or Python for modeling and analysis
Knowledge of modern processor microarchitecture and design tradeoffs
Strong analytical and problem-solving skills with attention to detail
Excellent communication skills and ability to work in cross-functional teams
Strong candidates may also have experience with AI/ML accelerator architectures and dataflow optimization
RTL design and verification (Verilog/SystemVerilog)
Cycle-accurate simulation tools (gem5, SystemC, or custom simulators)
Power and performance analysis methodologies
ASIC design flow and physical design constraints
Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.)
Hands-on experience with tapeout and silicon bring-up
Base Compensation Range $200,000 - $265,000
Benefits Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of
$2,000/month
for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
How we’re different Etched believes in the
Bitter Lesson
. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
#J-18808-Ljbffr