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This team is at the forefront of technological innovation, specializing in the design, development, and production of CPUs for ByteDance data center servers. Leveraging a team of highly skilled engineers, researchers, and experts, the unit focuses on creating high-performance, energy-efficient, and reliable chips that power a wide range of electronic devices and systems.
Responsibilities
- Develop UVM based test bench
- Develop simulation methodology for automated and re-usable environments.
- Define and execute test plan towards coverage target
- Support performance verification, power-aware simulation, RTL / FW co-simulation, and GTL simulation.
- Improve and refine verification process
Qualifications
Minimum Qualifications :
- Bachelor of Science in Computer Science, Electrical Engineering, or related fields
- Industry experience as Design Verification Engineer
Preferred Qualifications :
- In-depth knowledge of UVM, System Verilog, Makefile, Perl, Python, and C / C++
- In-depth knowledge of AMBA CHI-E, ACE-lite 4 / 5 protocols, SMMU, IO Coherency, and Scheduler
- Experience with chip interlinking protocols like UCIe, CXL and CCIX
- Autonomous, result-oriented, milestone-driven, and a thorough approach to work
- Proven ability to work well in a team
- Have skills : NVMe, SR-IOV, S-IOV, and Compression algorithm
LI-MZ3
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Design Verification Engineer • San Jose, CA, United States
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