Position Overview: We are looking for a motivated and detail-oriented Junior Chip Top Layout Designer to join our image sensor analog layout team. This is an excellent opportunity for someone early in their career to gain hands-on experience in the physical design of advanced integrated circuits, particularly in the top-level layout of analog/mixed-signal or image sensor chips Responsibilities: Assist in the top-level layout integration of analog/mixed-signal ICs or image sensor chips under the guidance of senior engineers. Support floor planning, power grid planning, and signal routing across the chip. Perform layout verification tasks including DRC, LVS, and ERC using industry-standard tools. Collaborate with circuit designers and senior layout engineers to understand block-level requirements and integration constraints. Help prepare layout documentation and support tape-out activities. Learn and apply best practices in layout design for manufacturability, reliability, and performance. Requirements: • Bachelor’s degree in electrical engineering, Microelectronics, or a related field. • Familiarity with IC layout tools such as Cadence Virtuoso or similar. • Basic understanding of CMOS technology and analog/mixed-signal layout principles. • Strong attention to detail and willingness to learn. • Good communication and teamwork skills. Preferred: • Internship or academic project experience in IC layout or physical design. • Exposure to layout verification tools like Calibre or Assura. • Basic scripting knowledge (e.g., SKILL, Python) is a plus Annual base salary for this role in California, US is expected to be between $100,000 - $135,000. Actual pay will be determined on a number of factors such as relevant skills, education, experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability #J-18808-Ljbffr
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