HPR
Design Verification Engineer II
HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we're searching for a forward-thinking Design Verification Engineer II to help us build the future of capital markets infrastructure. As a Design Verification Engineer II at HPR, you will: Verify and maintain high-performance FPGA compute and networking systems used in electronic trading Contribute to the verification process from specification, test planning, and testbench development through execution and coverage closure Partner with design engineers to review and execute comprehensive test plans Create and maintain reusable verification components and testbenches written in SystemVerilog Help improve our verification processes, tools, and methodologies Required Qualifications BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related 2+ years of experience in design verification for FPGAs or ASICs Working knowledge of SystemVerilog for verification Comfortable working in a Linux environment Strong problem solving, debugging, and communication skills Desired Qualifications Exposure to constrained-random verification techniques and functional coverage Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi) Familiarity with computer architecture and digital design concepts Knowledge of networking protocols (IP, TCP, UDP) Some knowledge of C programming and scripting in Python and/or Perl This position requires being on-site at our office in Needham, MA full-time (5 days per week). HPR does not currently provide employment sponsorship.
HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we're searching for a forward-thinking Design Verification Engineer II to help us build the future of capital markets infrastructure. As a Design Verification Engineer II at HPR, you will: Verify and maintain high-performance FPGA compute and networking systems used in electronic trading Contribute to the verification process from specification, test planning, and testbench development through execution and coverage closure Partner with design engineers to review and execute comprehensive test plans Create and maintain reusable verification components and testbenches written in SystemVerilog Help improve our verification processes, tools, and methodologies Required Qualifications BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related 2+ years of experience in design verification for FPGAs or ASICs Working knowledge of SystemVerilog for verification Comfortable working in a Linux environment Strong problem solving, debugging, and communication skills Desired Qualifications Exposure to constrained-random verification techniques and functional coverage Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi) Familiarity with computer architecture and digital design concepts Knowledge of networking protocols (IP, TCP, UDP) Some knowledge of C programming and scripting in Python and/or Perl This position requires being on-site at our office in Needham, MA full-time (5 days per week). HPR does not currently provide employment sponsorship.