eTeam
Hardware Engineer
Location: Cedar Rapids, IA Duration: 12 months Job Responsibilities: Experience range - 6-15 years Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
Location: Cedar Rapids, IA Duration: 12 months Job Responsibilities: Experience range - 6-15 years Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow