Celestial AI
PIC Design Engineer
In this role, you will be a key part of the team responsible for the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs. Essential Duties and Responsibilities: Contribute to the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs. Contribute to PIC delivery, all the way from floor-planning and top-level block placement to micro-architecture, optical & electrical routing, and back-end DRC and LVS verification. Work in conjunction with broader analog, digital and packaging teams to drive PIC physical design in accordance with product requirements related to opto-electronic performance, signal integrity (SI) & power integrity (PI). Work closely with the rest of the Photonics team to optimize layout flows and add to existing software base for automated design and verification. Qualifications: Specialized Skills: Good grasp of fundamental photonics concepts and engineering design principles Experience with Silicon Photonics Process Design Kits and related best practices in the layout of photonic devices, sub-systems and full PICs. Experience with physical design packages (Cadence, Siemens Mentor, Klayout or similar), including layout automation within these tools using SKILL, Python or similar. Experience with layout verification tools for DRC, ERC and LVS (Calibre, Pegasus or similar). Familiarity with SI and PI-aware electrical routing for analog and digital blocks is a strong plus. Education Requirements: PhD in engineering or physics with concentration/experience in integrated photonics Attributes: Self-starter Creativity in problem-solving with strong attention to detail Thrives in a highly collaborative and dynamic work environment Has excellent oral and written communication skills Location: Santa Clara, CA For California Location: As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing. Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
In this role, you will be a key part of the team responsible for the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs. Essential Duties and Responsibilities: Contribute to the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs. Contribute to PIC delivery, all the way from floor-planning and top-level block placement to micro-architecture, optical & electrical routing, and back-end DRC and LVS verification. Work in conjunction with broader analog, digital and packaging teams to drive PIC physical design in accordance with product requirements related to opto-electronic performance, signal integrity (SI) & power integrity (PI). Work closely with the rest of the Photonics team to optimize layout flows and add to existing software base for automated design and verification. Qualifications: Specialized Skills: Good grasp of fundamental photonics concepts and engineering design principles Experience with Silicon Photonics Process Design Kits and related best practices in the layout of photonic devices, sub-systems and full PICs. Experience with physical design packages (Cadence, Siemens Mentor, Klayout or similar), including layout automation within these tools using SKILL, Python or similar. Experience with layout verification tools for DRC, ERC and LVS (Calibre, Pegasus or similar). Familiarity with SI and PI-aware electrical routing for analog and digital blocks is a strong plus. Education Requirements: PhD in engineering or physics with concentration/experience in integrated photonics Attributes: Self-starter Creativity in problem-solving with strong attention to detail Thrives in a highly collaborative and dynamic work environment Has excellent oral and written communication skills Location: Santa Clara, CA For California Location: As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing. Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.