Clearance Jobs
Senior Fpg Design Engineer
We have an outstanding contract (12 months, possible hire) position for a Senior FPGA Design Engineer to join a leading company located in the Camden, NJ surrounding area. Pay range: $90 - $115/hr. US citizenship is required. Candidate must have the ability to obtain and maintain a Secret Security Clearance. Basic hiring criteria: Bachelor of Science (BS) or Masters (MS) or Ph.D from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science) Minimum 3-5 years of experience designing FPGA products with VHDL Experience with Xilinx FPGAs and Vivado Experience with revision control systems Experience with Earned Value Management (EVM) Desired qualifications: Experience with mapping algorithms to architecture Experience in C++ (OOP) Experience with any of the protocols: Ethernet, TCP/IP, PCIe, NVMe, USB Experience with Xilinx SoC design with SDKs and PetaLinux OS Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult Good written, verbal, and presentation skills
We have an outstanding contract (12 months, possible hire) position for a Senior FPGA Design Engineer to join a leading company located in the Camden, NJ surrounding area. Pay range: $90 - $115/hr. US citizenship is required. Candidate must have the ability to obtain and maintain a Secret Security Clearance. Basic hiring criteria: Bachelor of Science (BS) or Masters (MS) or Ph.D from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science) Minimum 3-5 years of experience designing FPGA products with VHDL Experience with Xilinx FPGAs and Vivado Experience with revision control systems Experience with Earned Value Management (EVM) Desired qualifications: Experience with mapping algorithms to architecture Experience in C++ (OOP) Experience with any of the protocols: Ethernet, TCP/IP, PCIe, NVMe, USB Experience with Xilinx SoC design with SDKs and PetaLinux OS Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult Good written, verbal, and presentation skills