Clearance Jobs
PCB Layout Engineer Intern (Summer 2025)
Clearance Jobs, San Francisco, California, United States, 94102
Pcb Layout Engineer Intern
Internships at Astranis typically last for twelve weeks, and are hourly roles designed for students who are currently enrolled at a four-year university. As an Intern, you will have an amazing opportunity to work on hard problems - we pride ourselves on giving everyone at Astranis a chance to do meaningful work on challenging projects, no matter their seniority. Many past interns have designed and tested hardware/software that is heading to space on our first satellite, and many of them are now full-time employees at Astranis. If you have already graduated from a four-year university, please apply to be an Associate Engineer. Role: Placement and Routing of Printed Circuit Board (PCB) designs, with schematic and layout input from design engineers Routing of power, high speed digital, RF, and analog PCB designs Create schematic symbols from datasheets and engineers' requests Design physical footprints from specifications and 3D models Automate interaction between ECAD tool and PLM system Interface with PCB Fabrication and assembly vendors to asses technical capabilities, design stackups and implement design for manufacturing (DFM) Requirements: Currently pursuing a B.S., M.S. or Ph.D. in electrical engineering (or equivalent technical degree) Familiarity with Altium or similar ECAD design tools Basic knowledge of analog, RF, power and digital electronics design principles US Citizenship or Green Card Don't meet them all? Not a problem. Please apply even if you do not meet all these criteria. Bonus: Experience with scripting or automation Knowledge of PCB manufacturing capabilities and assembly processes The base pay for this position is $29.00 per hour. U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required (To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States, or other protected individual as defined by 8 U.S.C. 1324b(a)(3)).
Internships at Astranis typically last for twelve weeks, and are hourly roles designed for students who are currently enrolled at a four-year university. As an Intern, you will have an amazing opportunity to work on hard problems - we pride ourselves on giving everyone at Astranis a chance to do meaningful work on challenging projects, no matter their seniority. Many past interns have designed and tested hardware/software that is heading to space on our first satellite, and many of them are now full-time employees at Astranis. If you have already graduated from a four-year university, please apply to be an Associate Engineer. Role: Placement and Routing of Printed Circuit Board (PCB) designs, with schematic and layout input from design engineers Routing of power, high speed digital, RF, and analog PCB designs Create schematic symbols from datasheets and engineers' requests Design physical footprints from specifications and 3D models Automate interaction between ECAD tool and PLM system Interface with PCB Fabrication and assembly vendors to asses technical capabilities, design stackups and implement design for manufacturing (DFM) Requirements: Currently pursuing a B.S., M.S. or Ph.D. in electrical engineering (or equivalent technical degree) Familiarity with Altium or similar ECAD design tools Basic knowledge of analog, RF, power and digital electronics design principles US Citizenship or Green Card Don't meet them all? Not a problem. Please apply even if you do not meet all these criteria. Bonus: Experience with scripting or automation Knowledge of PCB manufacturing capabilities and assembly processes The base pay for this position is $29.00 per hour. U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required (To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States, or other protected individual as defined by 8 U.S.C. 1324b(a)(3)).