Meta Platforms
ASIC Implementation Engineer - Timing
Meta Platforms, Sunnyvale, California, United States, 94086
ASIC Implementation Engineer - Timing
Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. Responsibilities
Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes Perform STA for full chip and Physical partition blocks using PrimeTime Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all FE-tools including (Synthesis, STA) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field 6+ years of experience with STA tools Experience with developing full chip flat & hierarchical timing constraints Experience with AOCV/POCV timing analysis, SI noise analysis Experience with running Static Timing Analysis for full chip using DMSA Knowledge of front-end and back-end ASIC flows Experience with communicating across functional internal teams and vendors Preferred Qualifications
Experience with SOC Design Integration & Front End Implementation Experience with Front End Synthesis tools such as Design Compiler, Genus Experience with Back End PD tools such as Fusion Compiler, Innovus Experience with Understanding RTL design using SystemVerilog or other HDL Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows Knowledge of Timing/physical libraries, SRAM Memories $142,000/year to $203,000/year + bonus + equity + benefits Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. Responsibilities
Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes Perform STA for full chip and Physical partition blocks using PrimeTime Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all FE-tools including (Synthesis, STA) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field 6+ years of experience with STA tools Experience with developing full chip flat & hierarchical timing constraints Experience with AOCV/POCV timing analysis, SI noise analysis Experience with running Static Timing Analysis for full chip using DMSA Knowledge of front-end and back-end ASIC flows Experience with communicating across functional internal teams and vendors Preferred Qualifications
Experience with SOC Design Integration & Front End Implementation Experience with Front End Synthesis tools such as Design Compiler, Genus Experience with Back End PD tools such as Fusion Compiler, Innovus Experience with Understanding RTL design using SystemVerilog or other HDL Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows Knowledge of Timing/physical libraries, SRAM Memories $142,000/year to $203,000/year + bonus + equity + benefits Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.