Senior Substrate Layout Design engineer
Piper Companies - Saratoga, California, us, 95071
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Overview
Senior Substrate Layout Design engineer
role at
Piper Companies 1 day ago Be among the first 25 applicants Join to apply for the
Senior Substrate Layout Design engineer
role at
Piper Companies Piper Companies is seeking a
Senior Substrate Layout Designer
who will be responsible for leading the design of advanced multi-die substrate packages. The layout designer will be
onsite 5 days
a week in
Saratoga, CA.
Check all associated application documentation thoroughly before clicking on the apply button at the bottom of this description.
Responsibilities for the Substrate Layout Designer include:
Lead the end-to-end physical layout of high-density, multi-die substrate design. Design and optimize bump maps, breakout routing, via structures, and layer stack-ups. Collaborate with ASIC, signal integrity, and power teams to ensure clean escape routing and breakout strategies Evaluate routing feasibility in co-design environments, considering die floorplans and mechanical constraints. Drive DRC, DFM, and manufacturing rule checks to ensure fabrication readiness Interface with substrate vendors and OSATs for tape-out and manufacturability validation. Conduct technical reviews and iterate on layout improvements with internal and external stakeholders
Requirements for the Substrate Layout Designer include:
8+ years of experience in substrate layout design for high-performance IC packaging Proven experience expertise in organic substrate design from silicon to BGA Deep understanding of chiplet-based, multi-die, and advanced packaging (FPGA, CPU, CPU, MCM, CoWoS) Strong collaboration skills with ASIC, signal, and power teams Proficiency in Cadence Allegro APD and AutoCAD Experience working with OSATs and substrate supplies Bachelor’s degree in Electrical Engineering or equivalent experience.
Compensation for the Substrate Layout Designer includes:
Salary range: $190,000 - $255,000 Comprehensive benefits: Medical, Dental, Vision, 401k, PTO, holidays, and sick leave as required by law.
Keywords: Substrate layout, substrate, package substrate design, multi-die packaging, chiplet integration, CoWoS, MCM, BGA, FPGA, CPU, GPU, High-density interconnect, escape routing, signal integrity, power integrity, organic substrate, substrate tape-out, substrate DRC, cadence allegro APD, autocad, cadence SiP layout, EDA tools, Layout verification tools, ASIC, OSAT, mechanical co-design, floorplanning, design reviews
This job is open for applications on 7/25/2025. Applications for this job will be accepted for at least 30 days from the posting date.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
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