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Go to next page Description: The role involves providing customization spec to vendors and PPA comparison of different foundation IP (memories, std cells, GPIO, eFUSE) used in next gen consumer SOC products. It also extends to resolving foundation IP issues and enabling our design teams for execution.
The candidate needs to: - Circuit Design experience for std cells and memories
- Work with arch, design & physical design teams to determine customizations for all foundation IP that are product differentiators
- Perform IP PPA analysis and vendor comparisons
- Provide specs and requirements to vendors
- Be able to understand and debug verilog, gls, dft, power management/upf modeling IP issues and communicate fixes to the team.
- Compile and create IP usage guidelines based on commonly encountered problems.
- Be data oriented, able to crunch through bug tracking system, and have front-end expertise
- Be able to multitask and respond quickly to different teams
Profile Expectations: - CS or EE/CE degree
- 5 years' experience in semiconductor companies
- Minimum 2 years of experience with foundation IP development
- Preferred knowledge of std cell and memory design including tools and flows used for characterization , familiarity with lib template generation etc.
- Knowledge of RTL to GDS flow
- Scripting with preference on python knowledge
- Strong communication skills
- bility to work independently
- Resourceful and solution driven individual
See details and apply
Foundation IP Engineer
