Arteris
Senior/Staff Design Verification Engineer
Arteris - Austin, Texas, us, 78716
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Overview
Join to apply for the
Senior/Staff Design Verification Engineer
role at
Arteris Join to apply for the
Senior/Staff Design Verification Engineer
role at
Arteris Get AI-powered advice on this job and more exclusive features. Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a
Senior/Staff
Design Verification Engineer
at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.
You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.
You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.
Key Responsibilities:
Advanced UVM based test bench development and debugging Defining, documenting, developing, and executing RTL verification test/coverage at system level Performance verification and power-aware verification Triaging Regressions, Debugging RTL designs in Verilog and System Verilog Help improve and refine verification process, methodology, and metrics UVM expertise on complex SoC projects from test bench development to verification closure
Experience Requirements / Qualifications:
5 or more years of design and verification experience and a plus in interconnect verification experience Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript Strong RTL (Verilog) and UVM/C test bench debugging skills Experience integrating vendor provided VIPs for unit and system level verification Experience with Arm AMBA protocols This opportunity involves high performance, low power designs on a highly visible project
Education Requirements:
MS degree in EE, CS, or equivalent preferred. BS degree minimum.
Estimated Annual Base Salary:
$150,000 to $200,000 annually
About Arteris :
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Computer Hardware Manufacturing, Software Development, and Semiconductor Manufacturing Referrals increase your chances of interviewing at Arteris by 2x Get notified about new Senior Design Verification Engineer jobs in
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Senior/Staff Design Verification Engineer
role at
Arteris Join to apply for the
Senior/Staff Design Verification Engineer
role at
Arteris Get AI-powered advice on this job and more exclusive features. Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a
Senior/Staff
Design Verification Engineer
at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.
You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.
You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.
Key Responsibilities:
Advanced UVM based test bench development and debugging Defining, documenting, developing, and executing RTL verification test/coverage at system level Performance verification and power-aware verification Triaging Regressions, Debugging RTL designs in Verilog and System Verilog Help improve and refine verification process, methodology, and metrics UVM expertise on complex SoC projects from test bench development to verification closure
Experience Requirements / Qualifications:
5 or more years of design and verification experience and a plus in interconnect verification experience Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript Strong RTL (Verilog) and UVM/C test bench debugging skills Experience integrating vendor provided VIPs for unit and system level verification Experience with Arm AMBA protocols This opportunity involves high performance, low power designs on a highly visible project
Education Requirements:
MS degree in EE, CS, or equivalent preferred. BS degree minimum.
Estimated Annual Base Salary:
$150,000 to $200,000 annually
About Arteris :
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Computer Hardware Manufacturing, Software Development, and Semiconductor Manufacturing Referrals increase your chances of interviewing at Arteris by 2x Get notified about new Senior Design Verification Engineer jobs in
Austin, TX . Austin, TX $130,355.00-$221,603.00 1 day ago Senior ASIC Front End Infrastructure Engineer
Austin, TX $184,000.00-$356,500.00 1 week ago Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Austin, TX $114,000.00-$166,000.00 2 weeks ago Austin, TX $136,000.00-$264,500.00 2 weeks ago Austin, TX $142,000.00-$203,000.00 2 weeks ago Senior ASIC Physical Design Engineer - High Performance Designs
Austin, TX $136,000.00-$264,500.00 2 weeks ago Austin, Texas Metropolitan Area 15 hours ago Austin, TX $173,000.00-$249,000.00 2 weeks ago Austin, TX $136,000.00-$310,500.00 1 day ago Austin, TX $129,800.00-$212,800.00 1 week ago Austin, TX $114,000.00-$166,000.00 2 weeks ago Austin, TX $104,960.00-$157,440.00 1 week ago Austin, TX $106,500.00-$162,000.00 1 week ago Austin, TX $136,000.00-$310,500.00 2 weeks ago Senior ASIC Physical Design and Timing Engineer
Austin, TX $136,000.00-$264,500.00 1 week ago Senior Performance IP Design Verification Engineer
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr