Tenstorrent
Sr. Staff CPU Physical Design Lead
Tenstorrent - Santa Clara, California, us, 95053
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Overview
Join to apply for the
CPU/AI/SOC Physical Design Lead
role at
Tenstorrent Join to apply for the
CPU/AI/SOC Physical Design Lead
role at
Tenstorrent Get AI-powered advice on this job and more exclusive features. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
If you want to know about the requirements for this role, read on for all the relevant information.
Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside with a group of highly experienced engineers across various domains of the CPU/AI chip.
This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities
Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization End to end tasks from flow development to sign-off Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
Experience & Qualifications
BS/MS/PhD in EE/ECE/CE/CS Minimum BS and 10+ years of experience in Physical Design Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc. Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling Strong programming skills in Tcl/Perl/Shell/Python Excellent understanding of logic design fundamentals and gate/transistor level implementation Exposure to DFT is an asset Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions Strong problem solving and debug skills across various levels of design hierarchies
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionOther IndustriesComputer Hardware Manufacturing Referrals increase your chances of interviewing at Tenstorrent by 2x Sign in to set job alerts for “CPU/AI/SOC Physical Design Lead” roles. Mountain View, CA $153,900.00-$223,250.00 1 day ago Santa Clara, CA $170,000.00-$230,000.00 1 month ago Mountain View, CA $170,100.00-$246,750.00 2 weeks ago Sr. Product Designer, Khan Kids (12-month contract, $80/hour, 40 hours/week)Senior Product Designer / Staff Product Designer San Mateo, CA $120,000.00-$180,000.00 1 month ago San Francisco Bay Area $50.00-$58.00 3 weeks ago Senior Product Designer, Core Experience Pleasanton, CA $110,000.00-$200,000.00 6 days ago Palo Alto, CA $154,000.00-$200,000.00 2 weeks ago Redwood City, CA $18,000.00-$20,000.00 1 week ago Lead Instructional Learning Designer (OEM) Pleasanton, CA $84,800.00-$141,000.00 1 week ago Palo Alto, CA $135,000.00-$160,000.00 3 weeks ago UX/UI Designer - Human Behavior and Carbon NeutralityUX/UI Designer - Human Behavior and Carbon Neutrality We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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CPU/AI/SOC Physical Design Lead
role at
Tenstorrent Join to apply for the
CPU/AI/SOC Physical Design Lead
role at
Tenstorrent Get AI-powered advice on this job and more exclusive features. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
If you want to know about the requirements for this role, read on for all the relevant information.
Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside with a group of highly experienced engineers across various domains of the CPU/AI chip.
This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities
Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization End to end tasks from flow development to sign-off Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
Experience & Qualifications
BS/MS/PhD in EE/ECE/CE/CS Minimum BS and 10+ years of experience in Physical Design Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc. Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling Strong programming skills in Tcl/Perl/Shell/Python Excellent understanding of logic design fundamentals and gate/transistor level implementation Exposure to DFT is an asset Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions Strong problem solving and debug skills across various levels of design hierarchies
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee informationand/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionOther IndustriesComputer Hardware Manufacturing Referrals increase your chances of interviewing at Tenstorrent by 2x Sign in to set job alerts for “CPU/AI/SOC Physical Design Lead” roles. Mountain View, CA $153,900.00-$223,250.00 1 day ago Santa Clara, CA $170,000.00-$230,000.00 1 month ago Mountain View, CA $170,100.00-$246,750.00 2 weeks ago Sr. Product Designer, Khan Kids (12-month contract, $80/hour, 40 hours/week)Senior Product Designer / Staff Product Designer San Mateo, CA $120,000.00-$180,000.00 1 month ago San Francisco Bay Area $50.00-$58.00 3 weeks ago Senior Product Designer, Core Experience Pleasanton, CA $110,000.00-$200,000.00 6 days ago Palo Alto, CA $154,000.00-$200,000.00 2 weeks ago Redwood City, CA $18,000.00-$20,000.00 1 week ago Lead Instructional Learning Designer (OEM) Pleasanton, CA $84,800.00-$141,000.00 1 week ago Palo Alto, CA $135,000.00-$160,000.00 3 weeks ago UX/UI Designer - Human Behavior and Carbon NeutralityUX/UI Designer - Human Behavior and Carbon Neutrality We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr