5 Star Global Recruitment Partners
Mixed Signal Verification Engineer
5 Star Global Recruitment Partners - Austin, Texas, us, 78716
Work at 5 Star Global Recruitment Partners
Overview
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Overview
About the job Mixed Signal Verification Engineer
Requirements
Minimum Qualifications
5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] Experience in Verilog/SystemVerilog coding Experience in Virtuoso Schematics tools Basic knowledge in Analog design Preferred Qualifications
Experience in UVM Experience in both Synopsys and Cadence tools is an advantage Additional Skills
Verification Methodologies and Tools : Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. Collaborative Environment : Ability to verify Analog/mixed-signal designs in a collaborative team environment. Communication : Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
Required Citizenship / Work Permit / Visa Status* Will sponsor H1-B
Must-Haves 5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification Experience in Verilog/System Verilog coding Experience in Virtuoso Schematics tools Experience in UVM Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] Experience in Verilog/SystemVerilog coding Experience in Virtuoso Schematics tools Basic knowledge in Analog design Preferred Qualifications
Experience in UVM Experience in both Synopsys and Cadence tools is an advantage Additional Skills
Verification Methodologies and Tools : Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. Collaborative Environment : Ability to verify Analog/mixed-signal designs in a collaborative team environment. Communication : Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
Required Citizenship / Work Permit / Visa Status* Will sponsor H1-B
Must-Haves 5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification Experience in Verilog/System Verilog coding Experience in Virtuoso Schematics tools Experience in UVM Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.