Apple Inc.
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.
All candidates should make sure to read the following job description and information carefully before applying. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You will develop verification methodology suitable for the IP, ensuring a scalable and portable environment. You will develop verification environment components such as stimulus, checkers, assertions, trackers, and coverage. Additionally, you will create verification plans for all features under your care, execute these plans, including design and environment bring-up, regression, and debugging test failures. You will learn to develop block, IP, and SoC level test-benches, track, and report DV progress using various metrics, including bugs and coverage. Minimum Qualifications
BS degree in a technical subject area with minimum 10 years of proven experience. Preferred Qualifications
Solid knowledge of OOP, SystemVerilog, and UVM. Experience developing scalable and portable test-benches. Experience with verification tools such as simulators, waveform viewers, automation, coverage collection, and gate-level simulations. Knowledge of power-aware (UPF) or similar verification methodologies. Proficiency in scripting languages such as Python, Perl, or TCL. Experience with serial protocols like PCIe or USB, or parallel protocols such as DDR, is a plus but not required. Knowledge of formal verification methodologies is a plus but not required. At Apple, base pay is part of our total compensation package and depends on skills, qualifications, experience, and location. The range for this role is between $171,600 and $302,200. Employees may also participate in stock programs, receive benefits including medical and dental coverage, retirement plans, discounts, educational reimbursement, and possibly bonuses or relocation assistance. Note: Benefits, compensation, and stock programs are subject to eligibility and plan terms. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.
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All candidates should make sure to read the following job description and information carefully before applying. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You will develop verification methodology suitable for the IP, ensuring a scalable and portable environment. You will develop verification environment components such as stimulus, checkers, assertions, trackers, and coverage. Additionally, you will create verification plans for all features under your care, execute these plans, including design and environment bring-up, regression, and debugging test failures. You will learn to develop block, IP, and SoC level test-benches, track, and report DV progress using various metrics, including bugs and coverage. Minimum Qualifications
BS degree in a technical subject area with minimum 10 years of proven experience. Preferred Qualifications
Solid knowledge of OOP, SystemVerilog, and UVM. Experience developing scalable and portable test-benches. Experience with verification tools such as simulators, waveform viewers, automation, coverage collection, and gate-level simulations. Knowledge of power-aware (UPF) or similar verification methodologies. Proficiency in scripting languages such as Python, Perl, or TCL. Experience with serial protocols like PCIe or USB, or parallel protocols such as DDR, is a plus but not required. Knowledge of formal verification methodologies is a plus but not required. At Apple, base pay is part of our total compensation package and depends on skills, qualifications, experience, and location. The range for this role is between $171,600 and $302,200. Employees may also participate in stock programs, receive benefits including medical and dental coverage, retirement plans, discounts, educational reimbursement, and possibly bonuses or relocation assistance. Note: Benefits, compensation, and stock programs are subject to eligibility and plan terms. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.
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