Apple Inc.
Cupertino, California, United States
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. You will develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Responsibilities include developing verification environment components such as stimulus, checkers, assertions, trackers, and coverage. You will also develop verification plans for features under your care, execute these plans, including design and environment bring-up, regression, and debugging test failures. Additionally, you will track and report DV progress using metrics like bugs and coverage. Minimum Qualifications
BS degree in a technical subject area with a minimum of 10 years of proven experience. Preferred Qualifications
Solid knowledge of OOP, SystemVerilog, and UVM. Experience developing scalable and portable test-benches. Experience with verification tools such as simulators, waveform viewers, automation, coverage collection, and gate-level simulations. Knowledge of power-aware (UPF) verification methodology is a plus. Proficiency in scripting languages such as Python, Perl, or TCL. Experience with serial protocols like PCIe or USB, and parallel protocols such as DDR, is a plus. Knowledge of formal verification methodologies is a plus but not required. At Apple, base pay is part of a total compensation package, ranging from $181,100 to $318,400, depending on skills, qualifications, experience, and location. Employees may participate in stock programs, receive benefits like medical coverage, retirement plans, discounts, educational reimbursement, bonuses, and relocation assistance. Learn more about Apple Benefits. Apple is an equal opportunity employer committed to diversity and inclusion, promoting equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.
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In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. You will develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Responsibilities include developing verification environment components such as stimulus, checkers, assertions, trackers, and coverage. You will also develop verification plans for features under your care, execute these plans, including design and environment bring-up, regression, and debugging test failures. Additionally, you will track and report DV progress using metrics like bugs and coverage. Minimum Qualifications
BS degree in a technical subject area with a minimum of 10 years of proven experience. Preferred Qualifications
Solid knowledge of OOP, SystemVerilog, and UVM. Experience developing scalable and portable test-benches. Experience with verification tools such as simulators, waveform viewers, automation, coverage collection, and gate-level simulations. Knowledge of power-aware (UPF) verification methodology is a plus. Proficiency in scripting languages such as Python, Perl, or TCL. Experience with serial protocols like PCIe or USB, and parallel protocols such as DDR, is a plus. Knowledge of formal verification methodologies is a plus but not required. At Apple, base pay is part of a total compensation package, ranging from $181,100 to $318,400, depending on skills, qualifications, experience, and location. Employees may participate in stock programs, receive benefits like medical coverage, retirement plans, discounts, educational reimbursement, bonuses, and relocation assistance. Learn more about Apple Benefits. Apple is an equal opportunity employer committed to diversity and inclusion, promoting equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.
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