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Sr Principal DFT Application Engineer
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Cadence 1 week ago Be among the first 25 applicants Join to apply for the
Sr Principal DFT Application Engineer
role at
Cadence Get AI-powered advice on this job and more exclusive features. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Prior experience with Cadence tools and flows is highly desirable Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment
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Sr Principal DFT Application Engineer
role at
Cadence 1 week ago Be among the first 25 applicants Join to apply for the
Sr Principal DFT Application Engineer
role at
Cadence Get AI-powered advice on this job and more exclusive features. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Prior experience with Cadence tools and flows is highly desirable Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment
We’re doing work that matters. Help us solve what others can’t. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Software Development Referrals increase your chances of interviewing at Cadence by 2x Get notified about new Principal Application Engineer jobs in
Austin, TX . Austin, TX $141,200.00-$338,500.00 6 days ago Code-Obsessed Problem Solver & PHP Hacker, Elite Code Hacker, Senior Full Stack Engineer, Senior Software Engineer-Laravel/PHP, Partner Success Manager & Sales Development Representative
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Austin, TX $140,960.00-$193,820.00 6 days ago Austin, TX $134,000.00-$241,900.00 21 hours ago Senior Software Engineer - Infrastructure
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Austin, TX $125,000.00-$160,000.00 1 month ago Austin, TX $143,000.00-$219,400.00 4 days ago Senior Deep Learning Compiler Engineer - XLA
Austin, TX $148,000.00-$287,500.00 15 hours ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr