Cadence
Cadence is seeking a SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). The candidate should have intimate knowledge and hands-on experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG). The role requires following systematic, quality-metrics driven ATPG pattern generation. Hands-on knowledge of synthesis, verification and debugging Verilog testbenches is highly desirable.
Responsibilities
Drive DFT insertion flows and perform basic scan chain insertion using synthesis or other software tools Implement and evaluate compression scan insertion, LBIST and other scan technologies Apply MBIST concepts to ensure memory test coverage Develop and optimize ATPG to achieve design test coverage goals Debug and analyze failures to improve fault coverage Verify ATPG testbenches and debug root causes of simulation mis-compares Work with JTAG 1149.1/6, IEEE 1500 and IEEE 1687 interfaces as applicable Collaborate with Architecture, Design and cross-functional teams; communicate with internal and external customers Work independently to complete DFT tasks and meet project timelines Demonstrate strong problem-solving skills, discipline, thoroughness and a methodical approach Qualifications
5-15 years of professional experience in SoC/ASIC Digital Design with a focus on Design for Test (DFT) Intimate knowledge of DFT insertion flows and basic scan chain insertion Experience with compression scan technologies, MBIST and ATPG Expertise in ATPG to meet design test coverage goals and debugging of ATPG testbenches Verification and debugging of testbenches; root cause analysis of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE 1500 and IEEE 1687 Bonus: timing analysis and equivalency checks Ability to work in a collaborative team environment and with stakeholders across cross-functional teams Prior experience with Cadence tools and flows is highly desirable We’re doing work that matters. Help us solve what others can’t.
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Drive DFT insertion flows and perform basic scan chain insertion using synthesis or other software tools Implement and evaluate compression scan insertion, LBIST and other scan technologies Apply MBIST concepts to ensure memory test coverage Develop and optimize ATPG to achieve design test coverage goals Debug and analyze failures to improve fault coverage Verify ATPG testbenches and debug root causes of simulation mis-compares Work with JTAG 1149.1/6, IEEE 1500 and IEEE 1687 interfaces as applicable Collaborate with Architecture, Design and cross-functional teams; communicate with internal and external customers Work independently to complete DFT tasks and meet project timelines Demonstrate strong problem-solving skills, discipline, thoroughness and a methodical approach Qualifications
5-15 years of professional experience in SoC/ASIC Digital Design with a focus on Design for Test (DFT) Intimate knowledge of DFT insertion flows and basic scan chain insertion Experience with compression scan technologies, MBIST and ATPG Expertise in ATPG to meet design test coverage goals and debugging of ATPG testbenches Verification and debugging of testbenches; root cause analysis of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE 1500 and IEEE 1687 Bonus: timing analysis and equivalency checks Ability to work in a collaborative team environment and with stakeholders across cross-functional teams Prior experience with Cadence tools and flows is highly desirable We’re doing work that matters. Help us solve what others can’t.
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