TPI Global Solutions
System Verification Engineer
TPI Global Solutions, San Jose, California, United States, 95199
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Performance Modeling/Verification Engineer – Intermediate San Jose, CA - 100% Onsite role 12+ months Contract Key Skills & Requirements: Modeling/Verification: SystemC (TLM2) – must have TVM – must have UVM – required BFM (Bus Functional Models) – must have; experience developing BFMs & testbenches Focus on SystemC verification, UVM test cases & infra dev Memory Controller verification experience – preferred Hardware: FPGA – min 5 years Top 3 Skills: SystemC (TLM2) performance modeling UVM knowledge Interview Process: 2–3 rounds (45 mins each) Onsite interview preferred
if candidate is local Description: Develop, enhance, and maintain
SystemC/TLM2
models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware. Collaborate with cross teams to integrate models into tools used for system-level designs, ensuring proper functionality and performance. Identify
bottlenecks and performance issues
within models and work to optimize their performance to meet design specifications. Develop and execute testbenches
to
validate
the functionality and correctness of models, as well as participate in system-level testing and debugging. Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Cycle approximate performance models SV/UVM Functional and Performance Verification Experience and Education: 5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ; Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Seniority level
Seniority level Mid-Senior level Employment type
Employment type Contract Job function
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Performance Modeling/Verification Engineer – Intermediate San Jose, CA - 100% Onsite role 12+ months Contract Key Skills & Requirements: Modeling/Verification: SystemC (TLM2) – must have TVM – must have UVM – required BFM (Bus Functional Models) – must have; experience developing BFMs & testbenches Focus on SystemC verification, UVM test cases & infra dev Memory Controller verification experience – preferred Hardware: FPGA – min 5 years Top 3 Skills: SystemC (TLM2) performance modeling UVM knowledge Interview Process: 2–3 rounds (45 mins each) Onsite interview preferred
if candidate is local Description: Develop, enhance, and maintain
SystemC/TLM2
models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware. Collaborate with cross teams to integrate models into tools used for system-level designs, ensuring proper functionality and performance. Identify
bottlenecks and performance issues
within models and work to optimize their performance to meet design specifications. Develop and execute testbenches
to
validate
the functionality and correctness of models, as well as participate in system-level testing and debugging. Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Cycle approximate performance models SV/UVM Functional and Performance Verification Experience and Education: 5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ; Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Seniority level
Seniority level Mid-Senior level Employment type
Employment type Contract Job function
Job function Other Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at TPI Global Solutions by 2x Get notified about new System Verification Engineer jobs in
San Jose, CA . Santa Clara, CA $108,000.00-$212,750.00 6 days ago Santa Clara, CA $163,360.00-$245,040.00 1 day ago Mountain View, CA $110,000.00-$130,000.00 6 hours ago Palo Alto, CA $100,000.00-$200,000.00 1 month ago Milpitas, CA $60,000.00-$80,000.00 6 days ago Milpitas, CA $110,000.00-$200,000.00 1 day ago Mountain View, CA $109,000.00-$155,000.00 2 weeks ago Software Verification Engineer - MedTech
Mountain View, CA $165,000.00-$190,000.00 1 month ago Santa Clara, CA $168,000.00-$310,500.00 6 days ago Staff Systems Software Verification Engineer
San Jose, CA $78,000.00-$142,000.00 5 days ago Mountain View, CA $130,000.00-$135,000.00 1 day ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr