Astera Labs
Principal Design Verification Engineer
Astera Labs, San Jose, California, United States, 95123
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Principal Design Verification Engineer
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Astera Labs 1 week ago Be among the first 25 applicants Join to apply for the
Principal Design Verification Engineer
role at
Astera Labs Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.
Do not pass up this chance, apply quickly if your experience and skills match what is in the following description.
Job Description
We are seeking a
Principal Design Verification Engineer
with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
Key Responsibilities
Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification. Work with RTL designers to troubleshoot and resolve design issues. Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
Bachelor’s degree in Electrical Engineering (Master’s preferred). 8+ years of experience in SoC verification, particularly for server and networking applications. Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle. Proficiency with industry-standard simulators, version control, and regression systems. Strong debugging and coverage analysis skills. Experience developing and executing test sequences, generating stimuli, and identifying verification holes. Familiarity with verification of switching architectures, including packet processing and forwarding engines. Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand. Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators. Knowledge of Ethernet/PCIe switching and central buffer architectures.
The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Astera Labs by 2x Sign in to set job alerts for “Design Verification Engineer” roles. San Jose, CA $150,000.00-$230,000.00 4 days ago Santa Clara, CA $150,000.00-$250,000.00 4 days ago Cupertino, CA $129,800.00-$212,800.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $136,000.00-$204,000.00 5 days ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $175,000.00-$225,000.00 4 days ago Design Verification Engineer at Santa Clara, CA (Onsite) San Jose, CA $160,000.00-$240,000.00 4 days ago San Jose, CA $180,000.00-$240,000.00 4 days ago Mountain View, CA $107,900.00-$242,000.00 3 weeks ago Physical Design and Verification Engineer Santa Clara, CA $97,700.00-$182,624.00 2 days ago Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago San Jose, CA $140,000.00-$160,000.00 1 month ago Advanced Physical Design and Verification Engineer (7036) San Jose, CA $85,500.00-$134,000.00 2 days ago Mountain View, CA $107,900.00-$242,000.00 1 week ago ASIC Design Verification Engineer, Devices and Services Mountain View, CA $156,000.00-$229,000.00 1 day ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago San Jose, CA $129,400.00-$177,900.00 5 days ago Santa Clara, CA $161,250.00-$260,000.00 6 months ago San Jose, CA $150,000.00-$275,000.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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Principal Design Verification Engineer
role at
Astera Labs 1 week ago Be among the first 25 applicants Join to apply for the
Principal Design Verification Engineer
role at
Astera Labs Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.
Do not pass up this chance, apply quickly if your experience and skills match what is in the following description.
Job Description
We are seeking a
Principal Design Verification Engineer
with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
Key Responsibilities
Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification. Work with RTL designers to troubleshoot and resolve design issues. Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
Bachelor’s degree in Electrical Engineering (Master’s preferred). 8+ years of experience in SoC verification, particularly for server and networking applications. Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle. Proficiency with industry-standard simulators, version control, and regression systems. Strong debugging and coverage analysis skills. Experience developing and executing test sequences, generating stimuli, and identifying verification holes. Familiarity with verification of switching architectures, including packet processing and forwarding engines. Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand. Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators. Knowledge of Ethernet/PCIe switching and central buffer architectures.
The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionEngineering and Information Technology IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Astera Labs by 2x Sign in to set job alerts for “Design Verification Engineer” roles. San Jose, CA $150,000.00-$230,000.00 4 days ago Santa Clara, CA $150,000.00-$250,000.00 4 days ago Cupertino, CA $129,800.00-$212,800.00 2 weeks ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $136,000.00-$204,000.00 5 days ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago San Jose, CA $175,000.00-$225,000.00 4 days ago Design Verification Engineer at Santa Clara, CA (Onsite) San Jose, CA $160,000.00-$240,000.00 4 days ago San Jose, CA $180,000.00-$240,000.00 4 days ago Mountain View, CA $107,900.00-$242,000.00 3 weeks ago Physical Design and Verification Engineer Santa Clara, CA $97,700.00-$182,624.00 2 days ago Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago San Jose, CA $140,000.00-$160,000.00 1 month ago Advanced Physical Design and Verification Engineer (7036) San Jose, CA $85,500.00-$134,000.00 2 days ago Mountain View, CA $107,900.00-$242,000.00 1 week ago ASIC Design Verification Engineer, Devices and Services Mountain View, CA $156,000.00-$229,000.00 1 day ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago San Jose, CA $129,400.00-$177,900.00 5 days ago Santa Clara, CA $161,250.00-$260,000.00 6 months ago San Jose, CA $150,000.00-$275,000.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr