Arm
Overview
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Principal DFT Architect
role at
Arm .
The Principal DFT Architect within Arm’s Solutions Engineering Group DFT team plays a crucial role in implementing Design for Test (DFT) strategies for Systems on Chip (SoCs) across various sectors, including client, datacenter, automotive, and IoT. The team works in close partnership with Arm’s external partners and internal teams—from RTL, verification, physical implementation, and test engineering—throughout all project phases, from initial investigation to tape-out, as well as silicon testing and characterization on Automatic Test Equipment (ATE).
Responsibilities
Architect DFT solutions for SoCs that serve multiple lines of business.
Coordinate DFT requirements with SOC, IP, and product teams to ensure alignment and integration.
Implement and validate innovative DFT techniques on both SoCs and sub-systems.
Insert DFT logic at both the SoC and sub-system levels, validating all DFT features using industry-standard simulation tools.
Collaborate closely with multi-functional teams to support DFT RTL-level insertion, synthesis, scan insertion, place-and-route, static timing analysis, and timing closure.
Chip in to the development of ATE-targeted test patterns, validation processes, and silicon debug activities.
Work alongside test and product engineering teams to support silicon characterization and validation efforts.
Required Skills and Experience
Shown experience as a DFT Architect, with at least 15 years in Design for Test methodologies.
Demonstrated ability handling DFT architecture for complex SoCs in advanced technology nodes.
Expertise in critical DFT areas, including Siemens DFT tools, Streaming Scan Network (SSN), scan compression and insertion, memory BIST and repair schemes, logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate-level verification, silicon debug, and memory and scan diagnostics.
Experience in 2.5D and 3D test methodologies.
Proficiency in Verilog RTL and scripting languages such as TCL and/or Perl.
Nice To Have
Familiarity with SoC architectures, particularly multi-clock domains and low-power design practices.
Understanding of Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug solutions.
Background in high-performance design, implementation, and achieving timing convergence.
Experience in leading datacenter SoC projects.
Hands-on experience with DFT or equivalent tools from Cadence and/or Synopsys.
Effective cross-team and cross-location communication across geographies and time zones.
Strong analytical and debugging skills with a proactive, problem-solving mindset.
Salary Range $241,100-$326,100 per year
Accommodations At Arm, we want to build extraordinary teams. If you need an adjustment or accommodation during the recruitment process, please email accommodations@arm.com. By sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality.
Hybrid Working Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Details of what this means for each role will be shared upon application. In some cases, flexibility may be limited by local considerations, and we will collaborate to find the best solution. Please talk to us to learn more.
Equal Opportunities Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
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Principal DFT Architect
role at
Arm .
The Principal DFT Architect within Arm’s Solutions Engineering Group DFT team plays a crucial role in implementing Design for Test (DFT) strategies for Systems on Chip (SoCs) across various sectors, including client, datacenter, automotive, and IoT. The team works in close partnership with Arm’s external partners and internal teams—from RTL, verification, physical implementation, and test engineering—throughout all project phases, from initial investigation to tape-out, as well as silicon testing and characterization on Automatic Test Equipment (ATE).
Responsibilities
Architect DFT solutions for SoCs that serve multiple lines of business.
Coordinate DFT requirements with SOC, IP, and product teams to ensure alignment and integration.
Implement and validate innovative DFT techniques on both SoCs and sub-systems.
Insert DFT logic at both the SoC and sub-system levels, validating all DFT features using industry-standard simulation tools.
Collaborate closely with multi-functional teams to support DFT RTL-level insertion, synthesis, scan insertion, place-and-route, static timing analysis, and timing closure.
Chip in to the development of ATE-targeted test patterns, validation processes, and silicon debug activities.
Work alongside test and product engineering teams to support silicon characterization and validation efforts.
Required Skills and Experience
Shown experience as a DFT Architect, with at least 15 years in Design for Test methodologies.
Demonstrated ability handling DFT architecture for complex SoCs in advanced technology nodes.
Expertise in critical DFT areas, including Siemens DFT tools, Streaming Scan Network (SSN), scan compression and insertion, memory BIST and repair schemes, logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate-level verification, silicon debug, and memory and scan diagnostics.
Experience in 2.5D and 3D test methodologies.
Proficiency in Verilog RTL and scripting languages such as TCL and/or Perl.
Nice To Have
Familiarity with SoC architectures, particularly multi-clock domains and low-power design practices.
Understanding of Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug solutions.
Background in high-performance design, implementation, and achieving timing convergence.
Experience in leading datacenter SoC projects.
Hands-on experience with DFT or equivalent tools from Cadence and/or Synopsys.
Effective cross-team and cross-location communication across geographies and time zones.
Strong analytical and debugging skills with a proactive, problem-solving mindset.
Salary Range $241,100-$326,100 per year
Accommodations At Arm, we want to build extraordinary teams. If you need an adjustment or accommodation during the recruitment process, please email accommodations@arm.com. By sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality.
Hybrid Working Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Details of what this means for each role will be shared upon application. In some cases, flexibility may be limited by local considerations, and we will collaborate to find the best solution. Please talk to us to learn more.
Equal Opportunities Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
#J-18808-Ljbffr