Northrop Grumman
Staff Digital Engineer (FPGA or ASIC Design) - R10206036
Northrop Grumman, Baltimore, Maryland, United States, 21276
Overview
Staff Digital Engineer (FPGA or ASIC Design) - R10206036 at Northrop Grumman. Roles involve technical leadership in digital design engineering, FPGA and/or ASIC design/implementation, and new technology development. On-site: Linthicum and/or Annapolis Junction, MD. Responsibilities
Recognized as SME in digital design engineering, FPGA and/or ASIC design/implementation, and new technology development. Oversee/collaborate on digital designs involving FPGA, ASIC, digital subsystems design and architecture for diverse design activities and applications. Lead a digital design team of 3-4 engineers with carrying skill level; participate in staffing and recruiting as required. Work with peers and leads to build strategies to address critical skills pipeline, covering VHDL/FPGA, embedded firmware, digital board design and subsystems architecture; develop technical training/work options and improve team performance. Partner with program management and engineering leads to maintain program execution, tracking metrics, communication and continuous improvement. Support and maintain digital engineering processes and procedures to ensure compliance with industry and company standards, requirements, and best practices. Provide technical guidance related to process and training to staff. Location note:
This position will serve 100% on-site in Linthicum and/or Annapolis Junction, MD. Qualifications
Basic Qualifications
Bachelor’s degree with 12 years of experience, a Master’s degree with 10 years of experience or a PhD with 7 years of experience in Science, Technology, Engineering or Mathematics or related technical fields. Experience working in a fast-paced environment with multiple projects developed and deployed simultaneously. Demonstrated success working well within a team and adapting quickly to change. Knowledge of SystemVerilog, Verilog and/or VHDL. Experience with industry-standard FPGA design tools for IP integration, place-and-route, CDC such as Xilinx Vivado, Intel Quartus, and QuestaSim. Full product life cycle experience (requirements, design, implementation and test) of FPGA Design and/or ASIC Design. Experience with ASIC/FPGA design verification using hardware verification and debugging tools. Strong time management, written and verbal communication, and organizational skills. U.S. citizen with ability to obtain and maintain a security clearance. Preferred Qualifications
Master’s degree in STEM, Engineering Leadership, or equivalent. Familiarity with Xilinx and Intel FPGA technology. Familiarity with Agile methodologies (JIRA, Confluence). Experience with ASIC front-end design tools for synthesis, LEC, CDC. Experience with Verification IP integration and/or development. Experience with a coverage-driven verification methodology from planning through closure. Experience with STA constraints generation and timing closure. Experience with bus functional models. Active security clearance. Compensation and Benefits
Primary Level Salary Range: $169,100.00 - $253,700.00 The salary range is a general guideline. Northrop Grumman considers factors such as scope, responsibilities, candidate experience, education, skills, and market conditions. Overtime, shift differential, and discretionary bonuses may be offered where applicable. We provide health insurance, life and disability insurance, savings plan, holidays, and PTO. Other information
The application period is estimated to be 20 days from the posting date, subject to change. Northrop Grumman is an Equal Opportunity Employer. U.S. Citizenship is required for positions with government clearance and certain restricted positions. For our complete EEO and pay transparency statement, visit http://www.northropgrumman.com/EEO.
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Staff Digital Engineer (FPGA or ASIC Design) - R10206036 at Northrop Grumman. Roles involve technical leadership in digital design engineering, FPGA and/or ASIC design/implementation, and new technology development. On-site: Linthicum and/or Annapolis Junction, MD. Responsibilities
Recognized as SME in digital design engineering, FPGA and/or ASIC design/implementation, and new technology development. Oversee/collaborate on digital designs involving FPGA, ASIC, digital subsystems design and architecture for diverse design activities and applications. Lead a digital design team of 3-4 engineers with carrying skill level; participate in staffing and recruiting as required. Work with peers and leads to build strategies to address critical skills pipeline, covering VHDL/FPGA, embedded firmware, digital board design and subsystems architecture; develop technical training/work options and improve team performance. Partner with program management and engineering leads to maintain program execution, tracking metrics, communication and continuous improvement. Support and maintain digital engineering processes and procedures to ensure compliance with industry and company standards, requirements, and best practices. Provide technical guidance related to process and training to staff. Location note:
This position will serve 100% on-site in Linthicum and/or Annapolis Junction, MD. Qualifications
Basic Qualifications
Bachelor’s degree with 12 years of experience, a Master’s degree with 10 years of experience or a PhD with 7 years of experience in Science, Technology, Engineering or Mathematics or related technical fields. Experience working in a fast-paced environment with multiple projects developed and deployed simultaneously. Demonstrated success working well within a team and adapting quickly to change. Knowledge of SystemVerilog, Verilog and/or VHDL. Experience with industry-standard FPGA design tools for IP integration, place-and-route, CDC such as Xilinx Vivado, Intel Quartus, and QuestaSim. Full product life cycle experience (requirements, design, implementation and test) of FPGA Design and/or ASIC Design. Experience with ASIC/FPGA design verification using hardware verification and debugging tools. Strong time management, written and verbal communication, and organizational skills. U.S. citizen with ability to obtain and maintain a security clearance. Preferred Qualifications
Master’s degree in STEM, Engineering Leadership, or equivalent. Familiarity with Xilinx and Intel FPGA technology. Familiarity with Agile methodologies (JIRA, Confluence). Experience with ASIC front-end design tools for synthesis, LEC, CDC. Experience with Verification IP integration and/or development. Experience with a coverage-driven verification methodology from planning through closure. Experience with STA constraints generation and timing closure. Experience with bus functional models. Active security clearance. Compensation and Benefits
Primary Level Salary Range: $169,100.00 - $253,700.00 The salary range is a general guideline. Northrop Grumman considers factors such as scope, responsibilities, candidate experience, education, skills, and market conditions. Overtime, shift differential, and discretionary bonuses may be offered where applicable. We provide health insurance, life and disability insurance, savings plan, holidays, and PTO. Other information
The application period is estimated to be 20 days from the posting date, subject to change. Northrop Grumman is an Equal Opportunity Employer. U.S. Citizenship is required for positions with government clearance and certain restricted positions. For our complete EEO and pay transparency statement, visit http://www.northropgrumman.com/EEO.
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