Qualcomm
Company:
Qualcomm Atheros, Inc. Job Area:
Engineering Group, ASICS Engineering General Summary:
A Lead SOC Physical Design Engineer plays a crucial role in the development and implementation of products at Qualcomm. This role requires strong knowledge and experience with physical design tools (like Cadence or Synopsys), semiconductor processes, timing closure, clock tree synthesis, power optimization, and physical verification methodologies. In addition, effective communication and the ability to lead a multi-geo PD team are essential for success in this role.
Minimum Qualifications:
Bachelor’s degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Or Master’s degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
Or PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:
Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
12+ years of ASIC Physical design, physical verification, validation, integration, or related work experience.
5+ years of experience with physical design tools.
5+ years of experience with scripting tools and programming languages.
5+ years of experience with physical design verification methods.
4+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
Principal Duties and Responsibilities:
Physical Design: Leading and executing the physical design process of complex semiconductor chips, ensuring adherence to design specifications and requirements.
Floorplanning: Leading and driving the creation of chip floorplans, considering functionality, power, performance, area, and routing congestion to optimize the layout.
Timing Closure: Ensuring the chip meets timing requirements by optimizing clock tree synthesis, placement, and routing.
Place and Route: Leading and driving the placement and routing of logic gates and interconnects, optimizing for performance, power, and area.
Power Optimization: Implementing power-saving techniques and strategies to meet low-power design goals.
Physical Verification: Leading and guiding the conduction of DRC, LVS, ERC and other checks to ensure the physical design meets manufacturing requirements.
Power Integrity: Ensuring that the chip meets constraints for IR drop, electromigration, and ESD path resistance checks.
Collaboration: Working with design teams, CAD engineers, program management, IT and other cross-functional teams to achieve project goals and resolve design challenges.
Methodology Development: Leading the development and improvement of physical design and verification methodologies, flows, and tools to enhance efficiency and quality of chip designs (including AI-based approaches).
Team Leadership: Providing technical leadership and mentoring within the physical design team across multiple geographies.
Level of Responsibility:
Technical leadership and expertise in Physical Design and verification of complex semiconductor chips.
Provides supervision/guidance to other team members.
Decision-making is significant in nature and highly impacts program or project success.
Requires verbal and written communication skills to convey complex information; may require negotiation and influence with large groups or high-level constituents.
Has a high degree of influence over key organizational decisions and strategy.
Tasks often require multiple steps and extensive planning, problem-solving, and prioritization to complete effectively.
Equal Opportunity Notice:
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email disability-accommodations@qualcomm.com or call Qualcomm’s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.
EEO Employer:
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay range and Other Compensation & Benefits: $203,300.00 - $304,900.00. The above pay scale reflects the broad minimum to maximum pay scale for this job code in the posting location. Salary is one component of total compensation, which includes a discretionary bonus program and RSU grants. Benefits details are available from the recruiter.
If you would like more information about this role, please contact Qualcomm Careers.
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Qualcomm Atheros, Inc. Job Area:
Engineering Group, ASICS Engineering General Summary:
A Lead SOC Physical Design Engineer plays a crucial role in the development and implementation of products at Qualcomm. This role requires strong knowledge and experience with physical design tools (like Cadence or Synopsys), semiconductor processes, timing closure, clock tree synthesis, power optimization, and physical verification methodologies. In addition, effective communication and the ability to lead a multi-geo PD team are essential for success in this role.
Minimum Qualifications:
Bachelor’s degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Or Master’s degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
Or PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:
Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
12+ years of ASIC Physical design, physical verification, validation, integration, or related work experience.
5+ years of experience with physical design tools.
5+ years of experience with scripting tools and programming languages.
5+ years of experience with physical design verification methods.
4+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
Principal Duties and Responsibilities:
Physical Design: Leading and executing the physical design process of complex semiconductor chips, ensuring adherence to design specifications and requirements.
Floorplanning: Leading and driving the creation of chip floorplans, considering functionality, power, performance, area, and routing congestion to optimize the layout.
Timing Closure: Ensuring the chip meets timing requirements by optimizing clock tree synthesis, placement, and routing.
Place and Route: Leading and driving the placement and routing of logic gates and interconnects, optimizing for performance, power, and area.
Power Optimization: Implementing power-saving techniques and strategies to meet low-power design goals.
Physical Verification: Leading and guiding the conduction of DRC, LVS, ERC and other checks to ensure the physical design meets manufacturing requirements.
Power Integrity: Ensuring that the chip meets constraints for IR drop, electromigration, and ESD path resistance checks.
Collaboration: Working with design teams, CAD engineers, program management, IT and other cross-functional teams to achieve project goals and resolve design challenges.
Methodology Development: Leading the development and improvement of physical design and verification methodologies, flows, and tools to enhance efficiency and quality of chip designs (including AI-based approaches).
Team Leadership: Providing technical leadership and mentoring within the physical design team across multiple geographies.
Level of Responsibility:
Technical leadership and expertise in Physical Design and verification of complex semiconductor chips.
Provides supervision/guidance to other team members.
Decision-making is significant in nature and highly impacts program or project success.
Requires verbal and written communication skills to convey complex information; may require negotiation and influence with large groups or high-level constituents.
Has a high degree of influence over key organizational decisions and strategy.
Tasks often require multiple steps and extensive planning, problem-solving, and prioritization to complete effectively.
Equal Opportunity Notice:
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email disability-accommodations@qualcomm.com or call Qualcomm’s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.
EEO Employer:
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay range and Other Compensation & Benefits: $203,300.00 - $304,900.00. The above pay scale reflects the broad minimum to maximum pay scale for this job code in the posting location. Salary is one component of total compensation, which includes a discretionary bonus program and RSU grants. Benefits details are available from the recruiter.
If you would like more information about this role, please contact Qualcomm Careers.
#J-18808-Ljbffr