Veracity Software Inc
System on Chip Architect (ASIC / RISC‑V)
Veracity Software Inc, Salt Lake City, Utah, United States, 84193
System on Chip Architect (ASIC / RISC-V)
Locations: Salt Lake City, UT or Boise, ID (On-site, Full-Time)
Security Requirement: Must be a
US Citizen , ideally with
active U.S. security clearance
(or held within the last two years).
Our client develops secure, hardened system solutions—leveraging Client CPU designs, crypto cores, and purpose-built SoC architectures. These technologies are vital to safeguarding military systems and critical U.S. infrastructure against future threats.
Responsibilities
Lead a cross-functional engineering team (hardware, software, verification) to drive the design and production of a RISC‑V ASIC SoC, transitioning an existing RTL into a tape-out-ready, production-quality chip.
Serve as the primary technical liaison between pilot customers, internal teams, and external subcontractors to define functionality, use cases, and specifications.
Finalize and manage the microarchitecture definition, including specifications and verification plans covering performance, power, area, security, and cost.
Design and oversee a thorough verification strategy (testbench, functional, and performance validation) to maximize first-pass success.
Stay current with ASIC process and design advancements, integrating new methodologies where appropriate.
Drive the product roadmap, translating feature requirements into actionable sprints and deliverables.
Partner strategically with external collaborators to support development, marketing, and product sustainment.
Required Qualifications
8+ years of experience in ASIC design and architecture.
Proven track record in designing and fabricating ASICs.
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science or similar.
Expert in RTL coding (Verilog/VHDL), ASIC design flows, and EDA tools.
Deep knowledge of processor architectures, digital logic, clocking, low-power design, and ASIC methodologies (synthesis, place-and-route, timing closure).
Strong background in verification methodologies such as UVM/SystemVerilog.
Demonstrated ability to lead complex technical projects and teams.
Preferred Experience
Holds or recently held a US security clearance.
In-depth understanding of processing architectures and microprocessor market dynamics.
Familiarity with applied cryptography and cybersecurity in embedded systems/OT.
Must-Haves
On-site availability in Salt Lake City or Boise.
U.S. Citizenship.
Leadership experience in RISC‑V ASIC architecture and SoC development.
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Security Requirement: Must be a
US Citizen , ideally with
active U.S. security clearance
(or held within the last two years).
Our client develops secure, hardened system solutions—leveraging Client CPU designs, crypto cores, and purpose-built SoC architectures. These technologies are vital to safeguarding military systems and critical U.S. infrastructure against future threats.
Responsibilities
Lead a cross-functional engineering team (hardware, software, verification) to drive the design and production of a RISC‑V ASIC SoC, transitioning an existing RTL into a tape-out-ready, production-quality chip.
Serve as the primary technical liaison between pilot customers, internal teams, and external subcontractors to define functionality, use cases, and specifications.
Finalize and manage the microarchitecture definition, including specifications and verification plans covering performance, power, area, security, and cost.
Design and oversee a thorough verification strategy (testbench, functional, and performance validation) to maximize first-pass success.
Stay current with ASIC process and design advancements, integrating new methodologies where appropriate.
Drive the product roadmap, translating feature requirements into actionable sprints and deliverables.
Partner strategically with external collaborators to support development, marketing, and product sustainment.
Required Qualifications
8+ years of experience in ASIC design and architecture.
Proven track record in designing and fabricating ASICs.
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science or similar.
Expert in RTL coding (Verilog/VHDL), ASIC design flows, and EDA tools.
Deep knowledge of processor architectures, digital logic, clocking, low-power design, and ASIC methodologies (synthesis, place-and-route, timing closure).
Strong background in verification methodologies such as UVM/SystemVerilog.
Demonstrated ability to lead complex technical projects and teams.
Preferred Experience
Holds or recently held a US security clearance.
In-depth understanding of processing architectures and microprocessor market dynamics.
Familiarity with applied cryptography and cybersecurity in embedded systems/OT.
Must-Haves
On-site availability in Salt Lake City or Boise.
U.S. Citizenship.
Leadership experience in RISC‑V ASIC architecture and SoC development.
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