AMD
Principal Advanced Packaging Technology Engineer
AMD, San Jose, California, United States, 95199
Principal Advanced Packaging Technology Engineer
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Principal Advanced Packaging Technology Engineer
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AMD Get AI-powered advice on this job and more exclusive features. This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Overview
The role is responsible for advanced 2.5D & 3D IC packaging technology evaluation, design enablement, product development, and manufacturing bring-up for FPGA and ASIC products from concept through to production. Responsibilities
Define 2.5D & 3D IC advanced packaging technology and drive system-technology co-optimization (STCO) of FPGA and ASIC products at advanced nodes Collaborate with design, CAD, and PDK teams to enable EDA design and verification flows for 2.5D/3D IC packaging Support exploration and development of 3DIC and packaging technology roadmap Drive 2.5D & 3DIC technology validation and reliability assessment prior to production Drive product yield analysis and design enhancement through collaboration with foundry and design teams to meet product needs Qualifications
Proven expertise in 2.5D & 3D packaging technologies such as CoWoS, SoIC, InFO and WoW, including manufacturing, design rules and reliability requirements Hands-on design experience with major EDA tools for 3DIC product/package design, physical verification, signal/power integrity analysis, reliability and thermal validation In-depth understanding of 2.5D & 3D IC product roadmap, challenges and solutions including cost, power delivery, thermal management etc. Working experience in 2.5D & 3D IC testchip and product design and product yield improvement is desirable Experience in packaging substrate design and co-optimization with 3DIC architectures Familiarity with advanced silicon nodes (e.g. 3nm, 2nm) is preferred Strong analytical, problem solving, decision-making and communication skills Prior team leadership and management experience is a plus Academic Credentials
Bachelor’s degree in engineering or physical science is required; an advanced degree (MS or PhD) is preferred Location
San Jose, CA Benefits
Benefits offered are described: AMD benefits at a glance. Job Details
Seniority level: Mid-Senior level Employment type: Full-time Job function: Engineering Industry: Semiconductor Manufacturing AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. Applications from all qualified candidates are welcome and we will accommodate applicants’ needs under applicable laws.
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Join to apply for the
Principal Advanced Packaging Technology Engineer
role at
AMD Get AI-powered advice on this job and more exclusive features. This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Overview
The role is responsible for advanced 2.5D & 3D IC packaging technology evaluation, design enablement, product development, and manufacturing bring-up for FPGA and ASIC products from concept through to production. Responsibilities
Define 2.5D & 3D IC advanced packaging technology and drive system-technology co-optimization (STCO) of FPGA and ASIC products at advanced nodes Collaborate with design, CAD, and PDK teams to enable EDA design and verification flows for 2.5D/3D IC packaging Support exploration and development of 3DIC and packaging technology roadmap Drive 2.5D & 3DIC technology validation and reliability assessment prior to production Drive product yield analysis and design enhancement through collaboration with foundry and design teams to meet product needs Qualifications
Proven expertise in 2.5D & 3D packaging technologies such as CoWoS, SoIC, InFO and WoW, including manufacturing, design rules and reliability requirements Hands-on design experience with major EDA tools for 3DIC product/package design, physical verification, signal/power integrity analysis, reliability and thermal validation In-depth understanding of 2.5D & 3D IC product roadmap, challenges and solutions including cost, power delivery, thermal management etc. Working experience in 2.5D & 3D IC testchip and product design and product yield improvement is desirable Experience in packaging substrate design and co-optimization with 3DIC architectures Familiarity with advanced silicon nodes (e.g. 3nm, 2nm) is preferred Strong analytical, problem solving, decision-making and communication skills Prior team leadership and management experience is a plus Academic Credentials
Bachelor’s degree in engineering or physical science is required; an advanced degree (MS or PhD) is preferred Location
San Jose, CA Benefits
Benefits offered are described: AMD benefits at a glance. Job Details
Seniority level: Mid-Senior level Employment type: Full-time Job function: Engineering Industry: Semiconductor Manufacturing AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. Applications from all qualified candidates are welcome and we will accommodate applicants’ needs under applicable laws.
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