Mulya Technologies
Overview
Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. Qualifications and Preferred Skills
BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Job details
Seniority level Mid-Senior level Employment type Full-time Job function Design, Research, and Engineering Industries Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computer and Network Security Note: This posting reflects the responsibilities and qualifications for the Design Verification Engineer role with Mulya Technologies as described in the original listing. Other job postings and extraneous site content have been omitted for clarity.
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Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. Qualifications and Preferred Skills
BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Job details
Seniority level Mid-Senior level Employment type Full-time Job function Design, Research, and Engineering Industries Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computer and Network Security Note: This posting reflects the responsibilities and qualifications for the Design Verification Engineer role with Mulya Technologies as described in the original listing. Other job postings and extraneous site content have been omitted for clarity.
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