Mindlance
Job Duties
Soft IP Development for FPGAs using Verilog / SystemVerilog.
Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors
Work with Verification Engineers to verify IP and debug issues.
Participate in board bring up as well as system level integration.
Experience and Education
years of experience in digital design
RTL coding experience using Verilog and / or SystemVerilog
Strong in digital design, micro architecture, RTL development
Working experience with Xilinx FPGA and Vivado
Experience in Video domain (DisplayPort / MIPI / HDMI / SDI) is preferred
Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs / Solutions
Good understanding of system design aspects and its impact on performance and throughput
#J-18808-Ljbffr
Soft IP Development for FPGAs using Verilog / SystemVerilog.
Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors
Work with Verification Engineers to verify IP and debug issues.
Participate in board bring up as well as system level integration.
Experience and Education
years of experience in digital design
RTL coding experience using Verilog and / or SystemVerilog
Strong in digital design, micro architecture, RTL development
Working experience with Xilinx FPGA and Vivado
Experience in Video domain (DisplayPort / MIPI / HDMI / SDI) is preferred
Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs / Solutions
Good understanding of system design aspects and its impact on performance and throughput
#J-18808-Ljbffr