Tenstorrent Inc.
Sr. Staff Engineer, CPU MidCore RTL Design
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. We are growing our team and looking for contributors of all seniorities. This role focuses on defining and implementing the MidCore block for a high-performance CPU based on the RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. The role is hybrid, based in Austin, TX or Santa Clara, CA.
Who You Are
Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath.
Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
What We Need
Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU.
Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.
Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
Enhance RTL design environment, tools, and methodologies to improve development efficiency.
What You Will Learn
End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
Hands-on experience optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases.
Integration of open-source and industry-standard tools to improve RTL flows and results.
Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.
Compensation and Equal Opportunity Compensation ranges from $100k to $500k including base and variable targets. Experience, skills, education, background, and location impact the offer. Tenstorrent is an equal opportunity employer and provides a highly competitive compensation package and benefits.
Export control notice: This offer may be contingent upon eligibility to access U.S. export-controlled technology in accordance with U.S. regulations. If employment is not possible due to export laws, any offer may be rescinded.
#J-18808-Ljbffr
Who You Are
Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath.
Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
What We Need
Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU.
Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.
Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
Enhance RTL design environment, tools, and methodologies to improve development efficiency.
What You Will Learn
End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
Hands-on experience optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases.
Integration of open-source and industry-standard tools to improve RTL flows and results.
Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.
Compensation and Equal Opportunity Compensation ranges from $100k to $500k including base and variable targets. Experience, skills, education, background, and location impact the offer. Tenstorrent is an equal opportunity employer and provides a highly competitive compensation package and benefits.
Export control notice: This offer may be contingent upon eligibility to access U.S. export-controlled technology in accordance with U.S. regulations. If employment is not possible due to export laws, any offer may be rescinded.
#J-18808-Ljbffr