TEEMA
Overview
Job Title:
CAD Engineer Job ID:
82448 Location:
Santa Clara, California What you will be doing
Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results Manage/monitor CAD tool licenses, compute server, and storage usage, optimizing for efficiency and cost Handle PDK and standard cell installation, management, and modification Develop and maintain automated flows for improving the SoC design process Develop, enhance, and maintain analog, mixed signal, and digital front- and back-end flows Generate mixed signal/Analog .lib and SystemVerilog views Debug verification issues (LVS/DRC/ERC/PEX/EMI) for both digital and analog environments and work with designers in resolving them Interface and manage relationship with internal/external IT support vendors, server co-location vendors and CAD engineering vendors Work with EDA tool vendors to drive issues and enhancements to closure Develop, maintain, and enhance internal scripts and tools using Shell/Skill/Python/C Maintain data management systems and manage design data archiving Ensure Linux system and environment tool compatibility What you must have
Bachelor of Science in Electrical Engineering or equivalent 8+ years’ experience in CAD flow/environment management Expertise developing/using industry-standard ASIC tools and methodologies for construction (e.g. partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) Experience supporting custom ASIC design CAD tools (e.g. Cadence, Synopsis, Mentor etc) Familiarity with both digital and analog design flow revision control software (e.g. GIT, SOS) In-depth experience in Mixed Signal database and simulation environment using Virtuoso Experience with EDA license management, LSF and equivalent job schedulers, and cloud-based silicon development Strong knowledge of PDK installation/management/modification Experience in foundry management and tapeout flows Familiarity reading and writing Verilog or SystemVerilog Strong proficiency in programming languages such as C/C++, Perl, Python, and TCL Familiarity with Linux server architecture, configuration, administration, maintenance, and package management Familiarity with different operating systems (Redhat, Ubuntu, etc) Experience with NFS/SMB file protocols and how they operate in Mac, Windows, and Linux environments Excellent problem-solving skills and attention to detail Great interpersonal and communication skills Ability to work independently and collaboratively Experience with GPU drivers and GPU servers Salary/Rate Range:
$180,000.00 – $250,000.00 Thank you for your interest in this opportunity. If you are selected to move forward in the process, we will contact you directly. If you do not hear from us, we encourage you to continue visiting our website for other roles that may be a good fit.
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Job Title:
CAD Engineer Job ID:
82448 Location:
Santa Clara, California What you will be doing
Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results Manage/monitor CAD tool licenses, compute server, and storage usage, optimizing for efficiency and cost Handle PDK and standard cell installation, management, and modification Develop and maintain automated flows for improving the SoC design process Develop, enhance, and maintain analog, mixed signal, and digital front- and back-end flows Generate mixed signal/Analog .lib and SystemVerilog views Debug verification issues (LVS/DRC/ERC/PEX/EMI) for both digital and analog environments and work with designers in resolving them Interface and manage relationship with internal/external IT support vendors, server co-location vendors and CAD engineering vendors Work with EDA tool vendors to drive issues and enhancements to closure Develop, maintain, and enhance internal scripts and tools using Shell/Skill/Python/C Maintain data management systems and manage design data archiving Ensure Linux system and environment tool compatibility What you must have
Bachelor of Science in Electrical Engineering or equivalent 8+ years’ experience in CAD flow/environment management Expertise developing/using industry-standard ASIC tools and methodologies for construction (e.g. partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) Experience supporting custom ASIC design CAD tools (e.g. Cadence, Synopsis, Mentor etc) Familiarity with both digital and analog design flow revision control software (e.g. GIT, SOS) In-depth experience in Mixed Signal database and simulation environment using Virtuoso Experience with EDA license management, LSF and equivalent job schedulers, and cloud-based silicon development Strong knowledge of PDK installation/management/modification Experience in foundry management and tapeout flows Familiarity reading and writing Verilog or SystemVerilog Strong proficiency in programming languages such as C/C++, Perl, Python, and TCL Familiarity with Linux server architecture, configuration, administration, maintenance, and package management Familiarity with different operating systems (Redhat, Ubuntu, etc) Experience with NFS/SMB file protocols and how they operate in Mac, Windows, and Linux environments Excellent problem-solving skills and attention to detail Great interpersonal and communication skills Ability to work independently and collaboratively Experience with GPU drivers and GPU servers Salary/Rate Range:
$180,000.00 – $250,000.00 Thank you for your interest in this opportunity. If you are selected to move forward in the process, we will contact you directly. If you do not hear from us, we encourage you to continue visiting our website for other roles that may be a good fit.
#J-18808-Ljbffr