Mindlance
Overview
Top skills: RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Responsibilities
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IP's. Lead, and participate in, the design of leading edge SoCs in advanced digital CMOS processes. Contribute in all aspects of SoC design including: chip definition, architecture development and modeling, development of micro-architectural specifications, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure, interfacing with physical execution, software, and silicon bring-up teams. Experience and Education
SoC Design Knowledge and hands-on experience from industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with front end quality checks such as Lint, CDC, RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O standard interfaces. Roughly 10 years experience, but less is acceptable. Bachelors in electrical engineering or computer engineering is preferred. Ideal Candidate Attributes
Strong communication and documentation skills Good organizational, time management and multitasking skills Strong initiative and discipline to follow-through Technical leadership EEO
“Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
#J-18808-Ljbffr
Top skills: RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Responsibilities
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IP's. Lead, and participate in, the design of leading edge SoCs in advanced digital CMOS processes. Contribute in all aspects of SoC design including: chip definition, architecture development and modeling, development of micro-architectural specifications, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure, interfacing with physical execution, software, and silicon bring-up teams. Experience and Education
SoC Design Knowledge and hands-on experience from industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with front end quality checks such as Lint, CDC, RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O standard interfaces. Roughly 10 years experience, but less is acceptable. Bachelors in electrical engineering or computer engineering is preferred. Ideal Candidate Attributes
Strong communication and documentation skills Good organizational, time management and multitasking skills Strong initiative and discipline to follow-through Technical leadership EEO
“Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
#J-18808-Ljbffr