VIVA USA INC
Overview Title: ASIC/RTL Design Engineer – Onsite
Want to make an application Make sure your CV is up to date, then read the following job specs carefully before applying. Description: Top skills include RTL coding, TCL coding, Python coding, and understanding of CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Responsibilities
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IPs. Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes. Contribute to all aspects of SoC design: chip definition, architecture development and modeling, development of micro-architectural specifications, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure. Interfacing with physical execution, software, and silicon bring-up teams. Experience and Education
SoC design with knowledge and hands-on experience in industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with frontend quality checks such as Lint, CDC, RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O interface standards. Approximately 10 years of experience preferred, but less is acceptable. Bachelor’s degree in electrical engineering or computer engineering preferred. Strong communication and documentation skills, good organizational, time management and multitasking abilities, strong initiative and discipline to follow-through, technical leadership. Mandatory skills
CAD tools, synthesis, lint, CDC, RDC, PrimeTime IP, ARM cores, Ethernet, DDR, DMA, PCIE, SATA SoC design, chip definition, architecture development and modeling RTL design, ASIC design flow IP integration, debugging, verification, synthesis Physical execution, software, silicon bring-up I/O interfaces, microarchitectural specifications, logic implementation, verification, emulation, debugging, synthesis Equal Opportunity VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical or mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era or other veterans. Contact Details Account coordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008
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Want to make an application Make sure your CV is up to date, then read the following job specs carefully before applying. Description: Top skills include RTL coding, TCL coding, Python coding, and understanding of CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Responsibilities
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IPs. Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes. Contribute to all aspects of SoC design: chip definition, architecture development and modeling, development of micro-architectural specifications, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure. Interfacing with physical execution, software, and silicon bring-up teams. Experience and Education
SoC design with knowledge and hands-on experience in industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with frontend quality checks such as Lint, CDC, RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O interface standards. Approximately 10 years of experience preferred, but less is acceptable. Bachelor’s degree in electrical engineering or computer engineering preferred. Strong communication and documentation skills, good organizational, time management and multitasking abilities, strong initiative and discipline to follow-through, technical leadership. Mandatory skills
CAD tools, synthesis, lint, CDC, RDC, PrimeTime IP, ARM cores, Ethernet, DDR, DMA, PCIE, SATA SoC design, chip definition, architecture development and modeling RTL design, ASIC design flow IP integration, debugging, verification, synthesis Physical execution, software, silicon bring-up I/O interfaces, microarchitectural specifications, logic implementation, verification, emulation, debugging, synthesis Equal Opportunity VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical or mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era or other veterans. Contact Details Account coordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008
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